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| CXD3011R-1 CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD3011R-1 is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter and 1-bit DAC. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a builtin RAM Digital Signal Processor (DSP) Block * Playback mode which supports CAV (Constant Angular Velocity) * Frame jitter free * 0.5x to 32x continuous playback possible with a low external clock * Allows relative rotational velocity readout * Wide capture range playback mode * Spindle rotational velocity following method * Supports 1x to 32x playback by switching the built-in VCO * The bit clock, which strobes the EFM signal, is generated by the digital PLL. * Digital PLL master clock can be set to 2/3 the conventional one. * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 32x playback * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and Sub-Q data error detection * Digital CLV spindle servo (built-in oversampling filter) * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high accuracy * Digital audio interface outputs * Digital level meter, peak meter * Bilingual compatible * VCO control mode * Digital out can be generated from the audio serial inputs. 144 pin LQFP (Plastic) Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment function * Surf jump and surf brake functions supporting micro two-axis * Tracking filter: 6 series Focus filter: 5 series * Servo drive DAC output possible Digital Filter and DAC Blocks * Digital de-emphasis * Digital attenuation * 8fs oversampling filter * Adoption of a tertiary noise shaper * Supports double-speed playback Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD -0.3 to +4.4 * Input voltage VI -0.3 to +4.4 (VSS - 0.3 to VDD + 0.3) * Output voltage VO -0.3 to +4.4 * Storage temperature Tstg -40 to +125 * Supply voltage difference VSS - AVSS -0.3 to +0.3 VDD - AVDD -0.3 to +0.3 V V V V C V V Recommended Operating Conditions 3.0 to 4.0 V * Supply voltage VDD * Operating temperature Topr -20 to +75 C The VDD (min.) for the CXD3011R-1 varies according to the playback speed and built-in VCO selection. The VDD (min.) for the CXD3011R-1 under various conditions are as shown on the following page. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97Z40A91-PS CXD3011R-1 Maximum Operating Speed 36 35 +25C 34 33 +55C [Multiple] 32 +75C 31 30 29 28 27 3.0 3.1 3.2 3.3 3.4 3.5 [V] 3.6 3.7 3.8 3.9 4.0 The Maximum Operating Speed graph shows the playback speed VDD (min.) at various temperatures. The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W mode with DSPB = 1. However, the DA output for the 64-bit slot supports 16xspeed. -2- CXD3011R-1 Block Diagram RMUTO VPCO1 VPCO2 PCMDI LRCKI XTLO DTS0 XTSL XWO XTLI LMUTO BCKI : Asymmetry Correction 83 84 5 6 51 30 32 28 122 74 75 76 DAC Block MCKO 52 V16M 136 VCKI 135 FSTIO 57 C4M 58 C16M 59 VCTL 7 PDO 134 VCOI 132 Digital PLL Vari-Pitch double speed OSC Address generator Clock Generator 32K RAM 8Fs Digital Filter + 1 bit DAC 87 PWMLP 88 PWMLN 80 PWMRP 79 PWMRN 25 PSSL 29 DA16 (48PCM) Serial/parallel processor PCO 10 FILI 9 FILO 8 CLTV 11 RFAC 13 ASYI 15 ASYO 16 ASYE 24 WFCK 64 SCOR 65 EXCK 67 SBSO 66 SQCK 69 SQSO 68 EFM Demodulator Register VCOO 131 31 DA15 (48BCK) 33 DA14 (64PCM) 34 DA13 (64BCK) 35 DA12 (64LRCK) 38 to 42, DA011 44 to 49 to DA1 63 MUTE Priority encoder 8 MUX Sync protector D/A data processor Timing Generator1 Subcode P to W processor Subcode Q processor Error corrector Error Rate counter Peak detector Digital out 62 DOUT 61 MD2 MDS 118 MDP 117 MON 116 FSW 107 Noise Shaper PWMI 129 Signal Processor Block TEST 133 TES2 123 TES3 124 XRST 71 Servo Block ADIO 140 MIRR DFCT FOK RFDC 141 CE 142 TE 143 SE 2 FE 3 VC 4 OpAmp AnaSw A/D CONVERTER SERVO DSP FOCUS SERVO TRACKING SERVO SLED SERVO DAC OpAmp FOCUS TRACKING SLED 113 FAO 112 TAO 111 SAO Servo Interface 18-times oversampling filter Servo auto sequencer 98 DATA CLV processor Timing Generator2 CPU interface 100 CLOK 99 XLAT 95 SENS 102 COUT 103 MIRR 104 DFCT 105 FOK 22 43 60 94 135 17 137 93 81 82 115 23 50 77 101 121 12 139 86 78 85 110 114 DVDD1 AVDD1 AVDD5 DVDD3 AVDD2 DVSS1 DVSS4 AVSS2 AVSS5 DVDD4 AVDD6 AVDD3 DVSS2 DVSS5 AVSS3 DVDD5 DVDD2 AVDD4 DVSS3 -3- AVSS1 AVSS4 AVSS6 BSSD CXD3011R-1 Pin Configuration PWMRP PWMRN PWMLN PWMLP RMUTO LMUTO DVDD4 AVDD3 AVDD5 DVSS4 AVDD4 AVSS3 SENS AVSS4 COUT ATSK SCLK MIRR DVSS3 TESO AVSS5 CLOK DFCT DATA XLAT XTLO FSW FOK XTLI NC NC XWO NC NC 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC 109 AVSS6 110 SAO 111 TAO 112 FAO 113 BSSD 114 AVDD6 115 MON 116 MDP 117 MDS 118 LOCK 119 SSTP 120 DVSS5 121 DTS0 122 TES2 123 TES3 124 NC 125 NC 126 NC 127 NC 128 PWMI 129 DVDD5 130 VCOO 131 VCOI 132 TEST 133 PDO 134 VCKI 135 V16M 136 AVDD2 137 IGEN 138 AVSS2 139 ADIO 140 RFDC 141 CE 142 TE 143 NC 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 NC 71 XRST 70 SCSY 69 SQCK 68 SQSO 67 EXCK 66 SBSO 65 64 SCOR WFCK NC NC 63 MUTE 62 DOUT 61 MD2 60 DVDD3 59 58 C16M C4M 57 FSTIO 56 NC 55 NC 54 NC 53 NC 52 MCKO 51 XTSL 50 DVSS2 49 DA01 48 47 46 45 44 DA02 DA03 DA04 DA05 DA06 43 DVDD2 42 DA07 41 DA08 40 DA09 39 DA10 38 DA11 37 NC AVSS1 VPCO1 VPCO2 DVSS1 ASYI CLTV LRCKI DVDD1 RFAC DA16 VCTL LRCK PCMDI WDCK AVDD1 ASYO PSSL DA15 DA14 DA13 BIAS BCKI NC NC NC VC FILO FILI PCO NC -4- ASYE DA12 NC NC SE FE CXD3011R-1 Pin Description Pin No. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 22 23 24 25 26 27 28 29 30 31 32 33 34 35 38 39 40 Symbol SE FE VC VPCO1 VPCO2 VCTL FILO FILI PCO CLTV AVSS1 RFAC BIAS ASYI ASYO AVDD1 DVDD1 DVSS1 ASYE PSSL WDCK LRCK LRCKI DA16 PCMDI DA15 BCKI DA14 DA13 DA12 DA11 DA10 DA09 I I O O I O I O I O O O O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 I I I O 1, 0 I I I O O I O I O I 1, Z, 0 Analog 1, Z, 0 1, Z, 0 I/O Sled error signal input. Focus error signal input. Center voltage input. Wide-band EFM PLL VCO2 charge pump output. Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E command FCSW. Wide-band EFM PLL VCO2 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Multiplier VCO control voltage input. Analog GND. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). Analog power supply. Digital power supply. Digital GND. Asymmetry circuit on/off (low = off, high = on). Audio data output mode switching input (low: serial, high: parallel). D/A interface for 48-bit slot. Word clock f = 2Fs. D/A interface for 48-bit slot. LR clock f = Fs. LR clock input to DAC (48-bit slot). DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's complement, MSB first) when PSSL = 0. Audio data input to DAC (48-bit slot). DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0. Bit clock input to DAC (48-bit slot). DA14 output when PSSL = 1, 64-bit slot serial data output (two' complement, LSB first) when PSSL = 0. DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0. DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0. DA11 output when PSSL = 1, GTOP output when PSSL = 0. DA10 output when PSSL = 1, XUGF output when PSSL = 0. DA09 output when PSSL = 1, XPLCK output when PSSL = 0. -5- Description CXD3011R-1 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 74 75 76 77 78 79 Symbol DA08 DA07 DVDD2 DA06 DA05 DA04 DA03 DA02 DA01 DVSS2 XTSL MCKO FSTIO C4M C16M DVDD3 MD2 DOUT MUTE WFCK SCOR SBSO EXCK SQSO SQCK SCSY XRST XWO RMUTO LMUTO DVSS3 AVSS4 PWMRN O I O I O O O I O I I I I O O I O I/O O O O O O O O O O O I/O 1, 0 1, 0 Description DA08 output when PSSL = 1, GFS output when PSSL = 0. DA07 output when PSSL = 1, RFCK output when PSSL = 0. Digital power supply. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 DA06 output when PSSL = 1, C2PO output when PSSL = 0. DA05 output when PSSL = 1, XRAOF output when PSSL = 0. DA04 output when PSSL = 1, MNT3 output when PSSL = 0. DA03 output when PSSL = 1, MNT2 output when PSSL = 0. DA02 output when PSSL = 1, MNT1 output when PSSL = 0. DA01 output when PSSL = 1, MNT0 output when PSSL = 0. Digital GND. Crystal selection input. 1, 0 1, 0 1, 0 1, 0 Clock output. Inverted output of XTLI. Digital servo clock input/output. (2/3 frequency division for XTLI pin is internally connected.) 1/4 frequency division output for XTLI pin. Changes with variable pitch. 16.9344MHz output. Changes simultaneously with variable pitch. Digital power supply. Digital Out on/off control (low = off, high = on). 1, 0 Digital Out output. Mute (low: off, high: on). 1, 0 1, 0 1, 0 WFCK (Write Frame Clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. 1, 0 Sub-Q 80-bit, PCM peak and level data 16-bit outputs. SQSO readout clock input. GRSCOR resynchronization input. Normally low, resynchronization is executed when high. System reset. Reset when low. Audio DAC sync window open input. Normally high, window open when low. 1, 0 1, 0 Audio DAC right channel zero detection flag. Audio DAC left channel zero detection flag. Digital GND. Analog GND. 1, Z, 0 Audio DAC PWM output. Right channel, reversed phase. -6- CXD3011R-1 Pin No. 80 81 82 83 84 85 86 87 88 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 110 111 112 113 114 115 116 117 118 Symbol PWMRP AVDD4 AVDD5 XTLO XTLI AVSS5 AVSS3 PWMLP PWMLN AVDD3 DVDD4 SENS SCLK ATSK DATA XLAT CLOK DVSS4 COUT MIRR DFCT FOK TESO FSW AVSS6 SAO TAO FAO BSSD AVDD6 MON MDP MDS O O O O O O I I/O I/O I/O I/O O O O I I I I I O O O I O I/O 1, Z, 0 Description Audio DAC PWM output. Right channel, forward phase. Analog power supply. Master clock power supply. 1, 0 Master clock crystal oscillation circuit output. Master clock crystal oscillation circuit input. Master clock GND. Analog GND. 1, Z, 0 1, Z, 0 Audio DAC PWM output. Left channel, forward phase. Audio DAC PWM output. Left channel, reversed phase. Analog power supply. Digital power supply. 1, Z, 0 SENS output to CPU. SENS serial data readout clock input. Set to high when not used. Anti-shock pin. Set to low when not used. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. Digital GND. 1, 0 1, 0 1, 0 1, 0 Track count signal I/O. Mirror signal I/O. Defect signal I/O. Focus OK signal I/O. Test pin. Leave this open. 1, Z, 0 Spindle motor output filter switching output. GRSCOR output when $8 command SCOR SEL = high. Analog GND. Sled filter DAC analog output. Tracking filter DAC analog output. Focus filter DAC analog output. Constant current input for servo filter DAC analog output. Analog power supply. 1, 0 1, Z, 0 1, Z, 0 Spindle motor on/off control output. Spindle motor servo control output. Spindle motor servo control output. -7- CXD3011R-1 Pin No. 119 120 121 122 123 124 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 Symbol I/O Description GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = high. (See $3E.) Disc innermost track detection signal input. Digital GND. LOCK SSTP DVSS5 DTS0 TES2 TES3 PWMI DVDD5 VCOO VCOI TEST PDO VCKI V16M AVDD2 IGEN AVSS2 ADIO RFDC CE TE I/O I 1, 0 I I I I Test pin. Normally fixed to low. Test pin. Normally fixed to low. Test pin. Normally fixed to low. Spindle motor external pin input. Digital power supply. O I I O I O 1, 0 Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. flock = 8.6436MHz. Test pin. Normally fixed to low. 1, Z, 0 Analog EFM PLL charge pump output. Variable pitch clock input from the external VCO. fcenter = 16.9344MHz. Set VCKI to low when the external clock is not input to this pin. 1, 0 Wide-band EFM PLL VCO2 oscillation output. Analog power supply. I -- O I I I Connects the operational amplifier current source reference resistance. Analog GND. Operational amplifier output. RF signal input. Center servo analog input. Tracking error signal input. In the CXD3011R, the following pins are NC. Pins 1, 18 to 21, 36, 37, 53 to 56, 72, 73, 89 to 92, 108, 109, 125 to 128 and 144 Notes) * The 64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.) * RFCK is derived from the crystal accuracy, and has a cycle of 136s. (during normal speed) * C2PO represents the data error status. * XRAOF is generated when the 32K RAM exceeds the 28F jitter margin. -8- CXD3011R-1 Electrical Characteristics 1. DC Characteristics Item Input voltage (1) (VDD = AVDD = 3.3V 10%, Vss = AVss = 0V, Topr = -20 to +75C) Conditions Min. 0.7VDD 0.2VDD Schmitt input VI 5.5V 0.7VDD 0.2VDD 0.7VDD 0.2VDD 0.7VDD 0.2VDD VSS VSS VDD - 0.4 0 VDD - 0.4 0 VDD - 0.2 0 0 VDD VDD VDD 0.4 VDD 0.4 VDD 0.4 0.4 VDD 0.4 10 20 5 Typ. Max. Unit V V V V V V V V V V V V V V V V V V V A 3, 4, 5 A A 6 10 7, 10 12 7, 10 12 8 11 5 6 9 4 3 2 Applicable pins 1, 12 High level input voltage VIH (1) Low level input voltage VIL (1) Input voltage (2) High level input voltage VIH (2) Low level input voltage VIL (2) Input voltage (3) High level input voltage VIH (3) Low level input voltage VIL (3) Input voltage (4) Input voltage (5) Input voltage (6) Output voltage (1) High level input voltage VIH (4) VI 5.5V Low level input voltage VIL (4) Schmitt input Input voltage Input voltage VIN (5) Analog input VIN (6) Analog input High level output voltage VOH (1) IOH = -8mA Low level output voltage VOL (1) IOL = 8mA High level output voltage VOH (2) IOH = -4mA Low level output voltage VOL (2) IOL = 4mA High level output voltage VOH (3) IOH = -2mA Low level output voltage VOL (3) IOL = 4mA Low level output voltage VOL (4) IOL = 4mA Output voltage (2) Output voltage (3) Output voltage (4) Output voltage (5) Input leak current (1) Input leak current (2) High level output voltage VOH (5) IOH = -0.28mA VDD - 0.5 Low level output voltage VOL (5) IOH = 0.36mA ILI (1) ILI (2) ILO VI = 0 to 5.5V VI = 0.25VDD to 0.75VDD VO = 0 to 3.6V 0 -10 -20 -5 Tri-state pin output leak current Applicable pins 1 DTS0, TES2, TES3, TEST, PSSL 2 ASYE, VCKI 3 ATSK, DATA, MD2, PWMI, SSTP, XLAT, XTSL, PCMDI, XWO 4 CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST, BCKI, LRCKI 5 ASYI, BIAS, CLTV, FILI, IGEN, BSSD, RFAC, VCTL 6 CE, FE, SE, TE, VC, RFDC 7 ASYO, C16M, C4M, DA01 to DA16, DOUT, LRCK, MON, SBSO, SCOR, SQSO, WDCK, WFCK, PWMLP, PWMLN, PWMRP, PWMRN, RMUTO, LMUTO 8 FSW 9 MCKO 10 MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2 11 FILO 12 COUT, DFCT, FOK, LOCK, MIRR, FSTIO -9- CXD3011R-1 2. AC Characteristics (1) XTLI pin, VCOI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTLI and VCOI pins (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol tWHX tWLX tCX VIHX VILX tR, tF Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tCX tWHX tWLX VIHX VIHX x 0.9 XTLI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTLI and VCOI pins via a capacitor (Topr = -20 to +75C, VDD = AVDD = 3.3V 10%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p - 10 - CXD3011R-1 (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 3.3V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency Symbol fCK tWCK tSU tH tD tWL fT 750 65 7.5 30 30 30 30 750 0.65 Min. Typ. Max. 16 Unit MHz ns ns ns ns ns MHz ns kHz s EXCK SQCK pulse width tWT CNIN frequency fT CNIN pulse width tWT Only when $44 and $45 are executed. 1/fCK tWCK tWCK CLOK DATA XLAT EXCK SQCK CNIN tSU tH tD tWL tWT 1/fT SBSO SQSO tSU tH tWT - 11 - CXD3011R-1 (3) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) ... MSB ... LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK tSPW tDLS Min. Typ. Max. 16 Unit MHz ns s 31.3 15 (4) COUT, MIRR and DFCT pins Operating frequency Signal (VDD = AVDD = 3.3V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Unit kHz kHz kHz Conditions 1 2 3 COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.11VDD to 0.23VDD B * 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 12 - CXD3011R-1 (5) BCKI, LRCKI and PCMDI pins Item Input BCKI frequency Input BCKI pulse width Input data setup time Input data hold time Input LRCK setup time Input LRCK hold time (VDD = 3.3V 10%, Topr = -20 to +75C) Min. Typ. Max. 4.5 100 10 15 10 15 tWIB tWIB Symbol tBCK tWIB tIDS tIDH tILRH tILRS Unit MHz ns BCKI 50% tIDS tIDH PCMDI tILRH tILRS LRCKI - 13 - CXD3011R-1 DAC Analog Characteristics Measurement conditions (Ta = 25C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 384fs) Item S/N ratio THD + N Dynamic range Channel separation Output level Difference in gain between channels 1 Using "A" weighting filter 2 -60dB, 1kHz input Typ. 93 0.007 91 91 0.81 0.1 Unit dB % dB dB V (rms) dB Remarks (EIAJ) 1 (EIAJ) (EIAJ) 1, 2 (EIAJ) The analog characteristics measurement circuit is shown below. 47k PWMLP (PWMRP) 33k 33k 100p PWMLN (PWMRN) 33k 33k 1000p 39k 100p 15k 15k 15k 100p 8.2k 220p 8.2k 8.2k 100 10 100k 15k 0.1 768fs PWMLP PWMLN Analog 1ch Audio Circuit 2ch PWMRN SHIBASOKU (AM51A) TEST DISC DATA CXD3011R PWMRP Audio Analyzer Block diagram of analog characteristics measurement - 14 - CXD3011R-1 Servo Drive Analog Characteristics (VDD = AVDD = 3.0 to 4.0V, VSS = AVSS = 0V, Topr = -20 to +75C, BSSD pin is connected to AVDD via a 33k resistor.) When the load resistance is 200k or more Item Maximum output voltage Minimum output voltage Min. 0.9VDD VSS Typ. 0.97VDD 0.03VDD Max. VDD 0.1VDD Unit V V Applicable pins FAO, TAO, SAO FAO, TAO, SAO When the load resistance is 60k Item Maximum output voltage Minimum output voltage VSS Min. Typ. 0.90VDD 0.03VDD 0.1VDD Max. Unit V V Applicable pins FAO, TAO, SAO FAO, TAO, SAO - 15 - CXD3011R-1 Contents [1] CPU Interface 1-1. CPU Interface Timing ................................ 1-2. CPU Interface Command Table ............................ 1-3. CPU Command Presets ............................... 1-4. Description of SENS Signals ............................. [2] Subcode Interface 2-1. P to W Subcode Readout .............................. 2-2. 80-bit Sub-Q Readout ................................ [3] Description of Modes 3-1. CLV-N Mode .................................... 3-2. CLV-W Mode .................................... 3-3. CAV-W Mode .................................... 3-4. VCO-C Mode .................................... [4] Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit .................. 4-2. Frame Sync Protection ............................... 4-3. Error Correction ................................... 4-4. DA Interface Output ................................. 4-5. Digital Out ..................................... 4-6. Servo Auto Sequence ................................ 4-7. Digital CLV ..................................... 4-8. Playback Speed .................................. 4-9. DAC Block Playback Speed ............................. 4-10. DAC Block Input Timing ............................... 4-11. Asymmetry Compensation .............................. 4-12. Clock System .................................... [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System ................. 5-2. Digital Servo Block Master Clock (MCK) ........................ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ............... 5-4. E:F Balance Adjustment Function ........................... 5-5. FCS Bias Adjustment Function ............................ 5-6. AGCNTL Function ................................. 5-7. FCS Servo and FCS Search ............................. 5-8. TRK and SLD Servo Control ............................. 5-9. MIRR and DFCT Signal Generation .......................... 5-10. DFCT Countermeasure Circuit ............................ 5-11. Anti-Shock Circuit .................................. 5-12. Brake Circuit .................................... 5-13. COUT Signal .................................... 5-14. Serial Readout Circuit ................................ 5-15. Writing to the Coefficient RAM ............................ 5-16. DAC Output .................................... 5-17. Servo Status Changes Produced by the LOCK Signal .................. 5-18. Description of Commands and Data Sets ........................ 5-19. List of Servo Filter Coefficients ............................ 5-20. Filter Composition .................................. 5-21. TRACKING and FOCUS Frequency Response ..................... [6] Application Circuit .................................... Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect - 16 - 17 17 28 34 71 71 78 78 78 79 82 84 84 85 88 92 100 101 102 102 106 107 108 109 110 111 111 113 115 116 117 118 118 119 120 120 121 122 123 124 149 151 157 158 CXD3011R-1 [1] CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 30ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 16 bits 20 bits 32 bits 32 bits 28 bits 20 bits 28 bits 20 bits 20 bits - 17 - Command Table ($0X to 1X) Data 1 D17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT -- -- FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- -- FOCUS SEACH VOLTAGE UP -- ANTI SHOCK ON -- ANTI SHOCK OFF -- BRAKE ON -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- TRACKING GAIN UP FILTER SELECT 2 -- -- CXD3011R-1 --: Don't care D6 D5 D4 Data 2 Data 3 Data 4 Data 5 Address Register Command D23 to D20 D19 0 D18 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS CONTROL 0000 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- 0 1 -- -- 0 -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- 0 -- -- -- 0 -- 1 0 -- -- -- -- -- 0 - 18 - 1 0 -- -- 1 TRACKING CONTROL 0001 -- -- -- -- Command Table ($2X to 3X) Data 1 D17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 D5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- D4 -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) -- SLED KICK LEVEL (2 x basic value) -- SLED KICK LEVEL (3 x basic value) -- -- -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- D7 D6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- -- -- -- -- -- -- -- -- -- -- -- D14 D13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 1 1 Data 1 D17 0 0 1 1 1 0 1 0 D16 1 0 1 0 -- -- -- -- D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE D6 D5 D4 Data 2 Data 3 Data 4 Data 5 Address Register 0 1 0 1 -- -- -- -- Command D23 to D20 D19 D18 0 0 1 1 2 TRACKING MODE 0010 -- -- -- - 19 - 0 0 0 0 -- Address Register Command D23 to D20 D19 D18 0 0 3 SELECT 0011 0 0 CXD3011R-1 Command Table ($340X) Address 3 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN CXD3011R-1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K00) SLED INPUT GAIN D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Address 4 Data 1 Data 2 Address 1 Address 2 Register 0 0 0 0 0 0 0 0 0000 1 1 1 1 1 1 1 1 Command D23 to D20 D19 to D16 D15 to D12 D11 - 20 - 3 SELECT 0011 0100 Command Table ($341X) Address 3 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L CXD3011R-1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K12) ANTI SHOCK INPUT GAIN 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K11) FOCUS OUTPUT GAIN 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Address 4 Data 1 Data 2 Address 1 Address 2 Register 0 0 0 0 0 0 0 0 0001 1 1 1 1 1 1 1 1 Command D23 to D20 D19 to D16 D15 to D12 D11 - 21 - 3 SELECT 0011 0100 Command Table ($342X) Address 3 Data 2 D4 D3 D2 D1 D0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K2E) NOT USED 0 KRAM DATA (K2F) NOT USED 1 D10 D7 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D6 D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 D9 D8 Address 4 Data 1 Address 1 Address 2 Register 0 0 0 0 0 0 0 0 0010 1 1 1 1 1 1 1 1 Command D23 to D20 D19 to D16 D15 to D12 D11 - 22 - 3 SELECT 0011 0100 CXD3011R-1 Command Table ($343X) Address 3 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 - 23 - 0011 3 SELECT 0011 0100 KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN CXD3011R-1 KRAM DATA (K3F) NOT USED Command Table ($344X) Address 3 D10 0 0 0 0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1) KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED CXD3011R-1 KRAM DATA (K4F) NOT USED 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register 0 0 0 0 0 0 Command D23 to D20 D19 to D16 D15 to D12 D11 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 24 - 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0100 1 1 1 1 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 3 SELECT 0011 0100 Command Table ($348X to 3FX) Address 3 D14 0 0 0 PGFS, PFOK, MIRR 0 0 DOUT Booster Surf Brake Booster Servo DAC output 0 0 0 0 0 0 0 0 0 0 0 0 0 A/D SEL SFBK1 SFBK2 0 0 0 0 Data 3 D4 D3 D2 D1 D0 -- FB3 TV3 FB2 FB1 TV2 TV1 -- TV0 FCS Bias Limit FCS Bias Data Traverse Center Data TV5 TV4 --: Don't care 0 0 0 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 0 0 0 THBON FHBON TLB1ON FLB1ON TLB2ON FAON TAON SAON FAOZ TAOZ SAOZ Data 2 D7 D6 D5 Data 1 D11 1 1 0 0 0 TV9 TV8 TV7 TV6 1 1 1 1 FB9 FB7 FB6 FB8 FB5 FB4 0 D10 D9 D8 0 0 0 COPY EMPH CAT DOUT DOUT DOUT WIN DOUT EN b8 D EN DMUT WOD EN EN2 0 1 1 0 0 Address 3 D15 D14 D13 D12 1 0 1 0 1 0 0 0 PGFS1 PGFS0 PFOK1 PFOK0 0 0 0 0 MRT1 MRT0 0 0 0 0 1 1 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Data 3 Address 1 Address 2 Register 1 1 1 1 1 1 Command D23 to D20 D19 to D16 D15 3 SELECT 0011 0100 - 25 - FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 CXD3011R-1 Command Table ($35X to 3FX) Address 2 D18 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 AGC4 XT4D XT2D DRR2 DRR1 DRR0 1 0 0 0 0 TLD2 TLD1 TLD0 1 SFID SFSK THID THSK 0 0 0 0 0 0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 1 1 1 0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 FBON FBSS FBUP FBV1 FBV0 0 0 0 0 0 1 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 0 1 1 1 TDZC DTZC TJ5 TJ3 TJ2 TJ1 0 TJ4 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 FT1 FT0 FS5 FS3 FS2 FS1 FS0 1 FS4 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FCS search, AGF TRK jump, AGT D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Address 1 Register Command D23 to D20 D19 0 0 0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel 0 Serial data read out FCS Bias, Gain, Surf jump/brake SJHD INBK MTI0 0 0 0 0 0 0 0 0 0 0 0 0 Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter LKIN COIN MDFI MIRI XT1D Filter ASFG FTQ LPAS SRO1 SRO0 AGHF 0 Clock, others 1 1 3 SELECT 0011 1 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT BTS1 BTS0 MRC1 MRC0 - 26 - F1NM F1DM F3NM F3DM TINM TIUM T3NM T3UM DF1S TLCD 1 1 1 1 CXD3011R-1 Command Table ($4X to EX) Data 1 D0 0 AS0 MT1 0 0 MT0 LSSL -- -- -- MT3 MT2 AS3 AS2 AS1 0 -- D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 2 Data 3 Data 4 Address D1 0 Register Command D3 D2 4 Auto sequence 0 1 5 TR0 0 0 0 0 0 -- -- 0 0 Blind (A, E), Brake (B), Overflow (C, G) 0 1 TR3 TR2 TR1 0 1 SD0 KF1 0 0 KF0 0 -- KF3 KF2 0 SD3 SD2 SD1 0 -- 0 1 -- -- 6 Sled KICK, BRAKE (D), KICK (F) 0 1 -- -- 7 4096 512 64 32 256 128 2048 1024 Auto sequence (N) track jump count setting 1 1 32768 16384 8192 0 KSL3 KSL2 0 1 ATT 4096 512 2048 1024 256 1 0 0 PWM MD 0 1 16 8 4 2 1 8 1 0 1 0 1 VP7 0 CM3 CM2 CM1 DCLV TB TP CLVS Gain VP6 32768 16384 8192 0 0 Mute DCLV DSPB ASEQ DPLL BiliGL BiliGL DAC FLFC XWOC ON/OFF ON/OFF ON/OFF ON/OFF MAIN SUB EMP MODE specification 0 1 0 CD- DOUT DOUT VCO VCO ASHS SOCT0 WSEL ROM Mute Mute-F SEL1 SEL2 KSL1 KSL0 0 VC01 VCO1 XVCO2 VCO2 CS1 CS0 THRU CS PLM3 PLM2 PLM1 PLM0 ATTCH ATD10 ATD9 ATD8 SEL 9 Function specification 1 0 DAC SYCOF ATT - 27 - 128 Gain Gain Gain Gain Gain Gain PCC1 PCC0 SFP3 MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 VP5 VP4 VP3 SFSL VC2C 1 CM0 EPWM SPDC ICAP A Audio CTRL 1 0 PCT1 PCT2 MCSL SOC2 DCOF FMUT BSBST BBSL 64 SFP2 VP2 32 SFP1 VP1 16 B Traverse monitor counter setting 1 0 8 4 2 1 SFP0 SRP3 SRP2 SRP1 SRP0 VP0 HIFC LPWR VPON VP CTL1 VP CTL0 0 0 INV Gain Gain FCSW VPCO CAV1 CAV0 --: Don't care C Spindle servo coefficient setting 1 1 D CLV CTRL 1 1 E SPD mode 1 1 CXD3011R-1 Command Table ($4X to EX) cont. Data 5 Data 1 D3 ERC4 0 0 0 -- -- -- -- 0 0 0 DIV4 0 -- -- 0 0 0 FSTIN 0 0 DAC DAC ZMUT ZDPL SMUTL SMUTR ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0 EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 SCOR SCSY SOCT1 SEL 0 0 -- -- --: Don't care D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 2 Data 3 Data 4 Data 6 Data 7 Register Command Address 8 MODE specification 1 0 0 0 9 Function specification 1 0 0 1 A Audio CTRL 1 0 1 0 C Spindle servo coefficient setting 1 1 0 0 1-3. CPU Command Presets Command Preset Table ($0X to 344X) Data 1 D17 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 Data 2 D15 -- Address 2 D17 0 0 0 D16 D15 D14 D13 D12 D11 -- -- -- D14 D13 D12 D11 -- -- -- -- -- -- -- 0 0 Data 1 D17 0 0 D16 -- -- -- D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 -- -- -- Data 2 Data 3 Data 4 D5 -- -- -- Data 4 Data 3 D10 -- D9 -- Address 3 D10 D9 D8 D7 D8 -- D7 -- D6 -- D5 -- Data 1 D6 D5 D4 See "Coefficient ROM Preset Values Table". D3 D4 -- D3 -- D4 -- -- -- D3 -- -- -- Data 5 D2 -- -- -- D1 -- -- -- Data 5 D2 -- D0 -- Data 2 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 x basic value) (Default) D0 -- -- -- FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF - 28 - 0 0 0 0 1 Address Register Command D23 to D20 D19 D18 0 FOCUS CONTROL 0000 0 1 TRACKING CONTROL 0001 0 2 TRACKING MODE 0010 0 Address Register Command D23 to D20 D19 D18 0011 0 Address 1 3 SELECT D23 to D20 D19 D18 CXD3011R-1 0011 0 Command Preset Table ($348X to 34FX) Address 3 Data 1 D12 0 0 PGFS, PFOK, MIRR CAV control DOUT Booster Surf Brake Booster Servo DAC output 0 0 0 0 1 Data 1 D10 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 0 0 0 Data 2 Data 3 D1 0 0 0 D0 0 0 0 FCS Bias Limit FCS Bias Data Traverse Center Data 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 D3 D2 D1 D0 D10 D9 D8 D7 D6 D5 D4 D14 0 0 0 1 1 0 0 Address 3 D15 D14 D13 1 1 0 1 1 1 0 D12 D11 0 0 0 1 1 D13 Data 2 Data 3 Address 1 Address 2 Register 1 1 1 1 1 1 Command D23 to D20 D19 to D16 D15 3 SELECT 0011 0100 - 29 - CXD3011R-1 Command Preset Table ($35X to 3FX) Address 2 D18 D3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter Filter Clock, others D2 D1 D0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 D17 D16 D15 D14 D13 D12 D11 D7 D6 D5 D4 D10 D9 D8 Data 1 Data 4 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 0 0 0 1 1 3 SELECT 0011 1 1 - 30 - 1 1 1 1 CXD3011R-1 Command Preset Table ($4X to EX) Data 1 D0 0 0 0 0 0 -- -- -- -- 0 0 -- 0 -- 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 -- -- D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 2 Data 3 Data 4 Address D1 0 0 Register Command D3 D2 4 Auto sequence 0 1 5 Blind (A, E), Brake (B), Overflow (C, G) 1 1 0 0 0 0 -- 0 0 0 0 1 1 0 0 -- -- 0 1 6 Sled KICK, BRAKE (D), KICK (F) 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 -- 7 Auto sequence (N) track jump count setting 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 MODE specification 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 --: Don't care 9 Function specification 1 0 A Audio CTRL 1 0 - 31 - Data 5 Data 1 Data 2 Data 3 Data 4 D3 0 0 0 0 B Traverse monitor counter setting 1 0 C Spindle servo coefficient setting 1 1 D CLV CTRL 1 1 E SPD mode 1 1 Data 6 D2 0 0 0 0 Data 7 D1 0 0 0 0 Register Command Address D0 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 0 0 D0 0 0 0 0 D3 0 0 -- -- D2 0 0 -- -- D1 0 0 -- -- D0 0 0 -- -- 8 MODE specification 1 0 0 0 9 Function specification 1 0 0 1 A Audio CTRL 1 0 1 0 CXD3011R-1 C Spindle servo coefficient setting 1 1 0 0 CXD3011R-1 Fix indicates that normal preset values should be used. - 32 - CXD3011R-1 - 33 - CXD3011R-1 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) ASEQ = 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 FZC AS TZC AGOK XAVEBSY SSTP FBIAS Count STOP SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS COMP COUT OV64 0 Output data length -- -- -- -- -- -- -- -- 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits -- -- -- -- -- -- -- -- $0X $1X $2X $38 $38 $30 to 37 $3A $3B to 3F $3904 $3908 $390C $391C $391D $391F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. - 34 - CXD3011R-1 Description of SENS Signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when the initial Reg.B number is input by CNIN. Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. COUT OV64 - 35 - CXD3011R-1 The meaning of the data for each address is explained below. $4X commands Register name Data 1 Command AS3 AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 4 Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move AS3 0 0 0 1 1 1 1 AS2 0 1 1 0 0 1 1 AS1 0 0 1 0 1 0 1 AS0 0 RXF 1 RXF RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To disable the MAX timer, set the MAX timer value to 0. $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms - 36 - CXD3011R-1 $6X commands Register name Data 1 KICK (D) SD3 SD2 SD1 SD0 KF3 SD3 23.2ms 11.6ms KF3 0.72ms Data 2 KICK (F) KF2 KF1 SD2 11.6ms 5.8ms KF2 0.36ms KF0 SD1 5.8ms 2.9ms KF1 0.18ms SD0 2.9ms 1.45ms KF0 0.09ms 6 Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) $7X commands Auto sequence track jump count setting Command Auto sequence track jump count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. - 37 - CXD3011R-1 $8X commands Command MODE specification Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 D0 VCO VCO CD- DOUT DOUT WSEL ASHS SOCT0 SEL1 SEL2 ROM Mute Mute-F Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Command bit D. out Mute F = 1 D. out Mute F = 0 Processing When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DOUT Mute D.out Mute F DOUT output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - dB 0dB OFF DA output for 48-bit slot DA output for 64-bit slot 0dB 0dB - dB - dB 0dB - dB 0dB 0dB - dB - dB See "Mute conditions" (1), (2), and (4) to (6) under $AX commands for other mute conditions. - 38 - CXD3011R-1 $8X commands contin. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit ASHS = 0 ASHS = 1 Function The command transfer rate to SSP is set to normal speed. The command transfer rate to SSP is set to half speed. See " 4-8. Playback Speed" for settings. Command bit SOCT0 0 1 1 SOCT1 -- 0 1 Processing Sub-Q is output from the SQSO pin. Each output signal is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) --: Don't care - 39 - CXD3011R-1 $8X commands contin. Command MODE specification Data 2 D3 D2 D1 D0 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 VCO VCO ASHS SOCT0 SEL1 SEL2 See the previous page. Command bit VCOSEL1 = 0 VCOSEL1 = 1 Processing Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed. This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0. Command bit KSL3 0 0 1 1 KSL2 0 1 0 1 Processing Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/1 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/2 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/4 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/8 frequency-divided. Command bit VCOSEL2 = 0 VCOSEL2 = 1 Processing Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed. This setting is valid only when the low-speed VCO is selected by VCO2CS. Command bit KSL1 0 0 1 1 KSL0 0 1 0 1 Processing Output of wide-band PLL VCO2 selected by VCO2CS is 1/1 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2CS is 1/2 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2CS is 1/4 frequency-divided. Output of wide-band PLL VCO2 selected by VCO2CS is 1/8 frequency-divided. - 40 - CXD3011R-1 $8X commands contin. Block Diagram of VCO Internal Path VCO1SEL No.1 VCO1 1/1 No.2 VCO1 Selector Selector 1/2 To DSP interior 1/4 No.3 VCO1 VCO1CS1, 0 1/8 KSL3, 2 No.4 VCO1 VCO1 internal path VCO2SEL Low-speed VCO2 1/1 Selector Selector 1/2 To DSP interior 1/4 High-speed VCO2 VCO2CS 1/8 KSL1, 0 VCO2 internal path - 41 - CXD3011R-1 $8X commands contin. Command D3 MODE specification Data 4 D2 D1 D0 VCO1 VCO1 XVCO2 VCO2 CS1 CS0 THRU CS Command bit VCO1CS1 VCO1CS0 0 0 1 1 0 1 0 1 Processing No.1 (Low-speed VCO for CXD3005R) No.2 (Middle-speed VCO for CXD3005R) No.3 (High-speed VCO for CXD3005R) No.4 The CXD3011R-1 has four multiplier PLL VCO1s, and this command selects one of these VCO1s. Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency. Command bit VCO2 THRU = 0 VCO2 THRU = 1 Processing V16M output is connected internally to VCKI. V16M output is not connected internally. Input the clock from VCKI. This command sets internal or external connection for the VCO2 used during CAV-W mode. Command bit VCO2 CS = 0 VCO2 CS = 1 Processing Low-speed wide-band PLL VCO2 is selected. High-speed wide-band PLL VCO2 is selected. The CXD3011R-1 has two wide-band PLL VCO2s, and this command selects one of these VCO2s. The block diagram for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to 3, VCO1CS0, VCO1CS1 and VCO2 CS is shown on the previous page. - 42 - CXD3011R-1 $8X commands contin. Command MODE specification Data 5 D3 ERC4 D2 D1 D0 D3 0 Data 6 D2 0 D1 0 D0 0 D3 FSTIN Data 7 D2 0 D1 0 D0 0 SCOR SCSY SOCT1 SEL Command bit ERC4 = 0 ERC4 = 1 Processing C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1. Command bit SCOR SEL = 0 FSW signal is output. Processing SCOR SEL = 1 GRSCOR (protected SCOR) is output. Used when outputting GRSCOR from the FSW pin Command bit SCSY = 0 SCSY = 1 No processing. Processing GRSCOR (protected SCOR) synchronization is applied again. Used to resynchronize GRSCOR. The rising edge signal of this command bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (Same as when SCSY = 1 is sent by the $8X command.) Command bit FSTIN = 0 Processing Clock switching for servo block; internally connected. (Preset) The clock with 2/3 frequency of XTLO pin is input to the servo block. FSTIO pin serves as the output pin which monitors the clock for the servo block. Clock switching for servo block; externally input. FSTIO pin serves as the input pin. The clock for servo block is input from FSTIO pin. FSTIN = 1 - 43 - CXD3011R-1 $9X commands Command Function specification Data 1 D3 D2 D1 D0 D3 BiliGL MAIN D2 BiliGL SUB Data 2 D1 FLFC D0 XWOC DCLV DSPB A.SEQ D.PLL ON-OFF ON-OFF ON-OFF ON-OFF Command bit CLV mode In CLVS mode Contents FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. When DCLV PWM and MD = 1 (Prohibited in CLV-W and CAV-W modes) When DCLV PWM and MD = 0 MDS = PWM polarity signal, carrier frequency of 132kHz MDP = PWM absolute value output (binary), carrier frequency of 132kHz MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz DCLV on/off = 0 In CLVP mode DCLV on/off = 1 (FSW, MON not required) In CLVS and CLVP modes When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1. Command bit DSPB = 0 DSPB = 1 Processing Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. Command bit DPLL = 0 DPLL = 1 Meaning RFPLL is analog. PDO, VCOI and VCOO are used. RFPLL is digital. PDO is high impedance. External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. - 44 - CXD3011R-1 $9X commands contin. Command bit XWOC 0 0 1 1 External pin XWO L H L H DAC sync window is not open. DAC sync window is open. Processing This is used to perform resynchronization to DAC. This command has the same function as the external pin XWO. Set to high or 1 for the unused external pin or unused command register, respectively. Command D3 Function specification DAC EMPH D2 Data 3 D1 SYCOF D0 0 DAC ATT Command bit DAC EMPH = 1 DAC EMPH = 0 Processing Applies digital de-emphasis. The emphasis constants are 1 = 50s and 2 = 15s when Fs = 44.1kHz. Turns digital de-emphasis off. Command bit DAC ATT = 1 DAC ATT = 0 Processing Identical digital attenuation control is used for both the left and right channels. When common attenuation data is specified, the attenuation values for the left channel are used. Independent digital attenuation control is used for both the left and right channels. Command bit SYCOF = 1 SYCOF = 0 LRCK asynchronous mode. Normal operation. Processing Set SYCOF = 0 in advance in order to resynchronize the DAC using $9 command XWOC or the external pin XWO. - 45 - CXD3011R-1 $9X commands contin. Command Function specification Data 4 D3 PLM3 D2 PLM2 D1 PLM1 D0 PLM0 * DAC play mode By controlling these command bits, the DAC output left channel and right channel can be output in 16 different combinations of left channel, right channel, left + right channel, and mute. The relationship between the commands and the outputs is shown in the table below. PLM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PLM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PLM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PLM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Left channel output Right channel output Mute L R L+R Mute L R L+R Mute L R L+R Mute L R L+R Mute Mute Mute Mute L L L L R R R R L+R L+R L+R L+R Remarks Mute Reverse Stereo Mono Note) The output data of L + R is (L + R)/2 to prevent overflow. - 46 - CXD3011R-1 $9X commands contin. Command D3 Function specification DAC SMUTL D2 DAC SMUTR Data 5 D1 ZMUT D0 ZDPL Command bit DAC SMUTL = 1 DAC SMUTL = 0 Left channel soft mute is on. Left channel soft mute is off. Processing Command bit DAC SMUTR = 1 DAC SMUTR = 0 Right channel soft mute is on. Right channel soft mute is off. Processing Command bit ZMUT = 1 ZMUT = 0 Zero detection mute is on. Zero detection mute is off. Processing Command bit ZDPL = 1 ZDPL = 0 Processing LMUTO and RMUTO are high during mute. LMUTO and RMUTO are low during mute. See the description of "Mute flag output" for the mute flag output conditions. Command Function specification Data 6 D3 0 D2 0 D1 0 D0 0 D3 DIV4 D2 0 Data 7 D1 0 D0 0 The master clock of the digital PLL is switched. The conventional mode or 2/3 mode of the conventional one can be selected. Command bit DIV4 = 0 DIV4 = 1 Processing Digital PLL master clock; conventional mode. (Preset) Digital PLL master clock; 2/3 mode. Note) Do not set DIV4 to 1 when DSPB = 0. - 47 - CXD3011R-1 $AX commands Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 PCT1 D2 PCT2 Data 2 D1 MCSL D0 SOC2 Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off. -12dB Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35 ms (during normal speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Normal mode Level meter mode Peak meter mode Normal mode x 0dB x 0dB Mute x 0dB C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Meaning PCM Gain ECC error correction ability Description of level meter mode (see Timing Chart 1-4.) * When the LSI is set to this mode, it performs digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are 15bit PCM data (absolute values) and an L/R flag. The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel. * The PCM data is reset and the L/R flag is reversed after one readout. Then maximum value measuring continues until the next readout. - 48 - CXD3011R-1 $AX commands contin. Description of peak meter mode (see Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value detection register is not reset by the readout. * To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute. * The Sub-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. * The final bit (L/R flag) of the 96-bit data is normally 0. * The pre-value hold and average value interpolation data are fixed to level (- ) for this mode. Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock is selected. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock is selected. Crystal = 384Fs (16.9344MHz) Note) See " 4-9. DAC Block Playback Speed". Command bit SOC2 = 0 SOC2 = 1 Processing The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. SENS output switching * This command enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. See " 1-4. Description of SENS Signals". When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. - 49 - CXD3011R-1 $AX commands contin. Data 3 Command Audio CTRL D3 DCOF D2 FMUT D1 BSBST D0 BBSL Command bit DCOF = 1 DCOF = 0 DC offset is off. DC offset is on. Processing Set DC offset to off when zero detection mute is on. Command bit FMUT = 1 FMUT = 0 Forced mute is on. Forced mute is off. Processing Command bit BSBST = 1 BSBST = 0 Bass boost on. Bass boost off. Processing Command bit BBSL = 1 BBSL = 0 Bass boost MAX. Bass boost MID. Processing - 50 - CXD3011R-1 $AX commands contin. Data 4 Command Audio CTRL D3 D2 D1 D0 D3 Data 5 D2 D1 D0 D3 Data 6 D2 D1 D0 ATTCH ATD10 ATD9 ATD8 ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0 SEL Command bit ATTCH SEL = 1 ATTCH SEL = 0 Processing Right channel attenuation data can be set. Left channel attenuation data can be set. Command bit ATD10 to 0 Attenuation data Meaning The attenuation data consists of 11 bits each for the left and right channels; the DAC ATT bit can be used to control the left and right channels with common attenuation data. When common attenuation data is specified, the attenuation values for the left channel are used. Attenuation data 400h 3FFh 3FEh : 001h 000h Audio output 0dB -0.0085dB -0.017dB : -60.206dB - The audio output, from 001h to 400h, is determined according to the following equation: Audio output = 20log Attenuation data 1024 [dB] $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT. - 51 - CXD3011R-1 $CX commands Command D3 Data 1 D2 D1 D0 D3 Data 2 D2 D1 D0 Description Gain Gain Gain Gain Gain Gain Spindle servo PCC1 PCC0 Valid only when DCLV = 1. coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 CLV CTRL ($DX) Gain CLVS Valid when DCLV = 1 or 0. The spindle servo gain is externally set when DCLV = 1 * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB Note) When DCLV = 0, the CLVS gain is as follows. When Gain CLVS = 0, GCLVS = -12dB. When Gain CLVS = 1, GCLVS = 0dB. * CLVP mode gain setting: GMDP : GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV1 0 0 1 Gain DCLV0 0 1 0 Command bit PCC1 0 0 1 1 PCC0 0 1 0 1 The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. GDCLV 0dB +6dB +12dB Processing * This command controls the VPCO1 and VPCO2 pin signals. Identical control can be performed for both VPCO1 and VPCO2 output with this setting. However, VPCO2 can also be set to high impedance with the $E command FCSW separately from this setting. - 52 - CXD3011R-1 $CX commands contin. * Processing for the $CX commands PCC1 and PCC0 and the $EX command FCSW is shown below. Command bit FCSW 0 0 0 0 1 1 1 1 PCC1 0 0 1 1 0 0 1 1 PCC0 0 1 0 1 0 1 0 1 Processing The VPCO1 pin signal is output and the VPCO2 pin is high impedance. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 pin output is low and the VPCO2 pin is high impedance. The VPCO1 pin output is high and the VPCO2 pin is high impedance. The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. Command Data 3 D3 D2 D1 D0 D3 Data 4 D2 D1 D0 Spindle servo SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0 coefficient setting Command bit SFP3 to 0 Processing Sets the frame sync forward protection times. The setting range is 1 to F (Hex). Command bit SRP3 to 0 Processing Sets the frame sync backward protection times. The setting range is 1 to F (Hex). See " 4-2. Frame Sync Protection" regarding frame sync protection. - 53 - CXD3011R-1 $CX commands contin. * The CXD3011R-1 can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. In order to output error rate data, set $C commands for C1 and C2 individually, and set SOCT0 and SOCT1 = 0 of $8 command. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses. See Timing Chart 2-6. Command Data 5 D3 D2 D1 D0 D3 Data 6 D2 D1 D0 Spindle servo EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 coefficient setting Error rate monitor commands Command bit EDC7 = 0 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 EDC7 = 1 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 Processing The [No C1 errors, pointer set] count is output when 1. The [One C1 error corrected, pointer reset] count is output when 1. The [No C1 errors, pointer set] count is output when 1. The [One C1 error corrected, pointer set] count is output when 1. The [Two C1 errors corrected, pointer set] count is output when 1. The [C1 correction impossible, pointer set] count is output when 1. 7350-frame count cycle mode1 when 0. 73500-frame count cycle mode2 when 1. The [No C2 errors, pointer reset] count is output when 1. The [One C2 error corrected, pointer reset] count is output when 1. The [Two C2 errors corrected, pointer reset] count is output when 1. The [Three C2 errors corrected, pointer reset] count is output when 1. The [Four C2 errors corrected, pointer reset] count is output when 1. The [C2 correction impossible, pointer copy] count is output when 1. The [C2 correction impossible, pointer set] count is output when 1. 1 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350 frames. 2 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 73500 frames. - 54 - CXD3011R-1 $DX commands Command CLV CTRL Data 1 D3 DCLV PWM MD D2 TB D1 TP D0 Gain CLVS See "$CX commands". Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Description Digital CLV PWM mode specified. Both MDS and MDP are used. CLV-W and CAV-W modes cannot be used. Digital CLV PWM mode specified. Ternary MDP values are output. CLV-W and CAV-W modes can be used. Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes. Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. - 55 - CXD3011R-1 $DX commands contin. Data 2 D3 VP7 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 D3 VP CTL1 Data 4 D2 VP CTL0 D1 0 D0 0 Command CLV CTRL Command bit VP0 to 7 The spindle rotational velocity is set. Processing Command bit VPCTL1 0 0 1 1 VPCTL0 0 1 0 1 Processing The setting of VP0 to 7 is multiplied by 1. The setting of VP0 to 7 is multiplied by 2. The setting of VP0 to 7 is multiplied by 3. The setting of VP0 to 7 is multiplied by 4. The above setting should be 0, 0 except for the CAV-W operating mode. The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n xl 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value 1: Multiple set by VPCTL0, 1 - 56 - CXD3011R-1 $DX commands contin. Command bit VP0 to 7 = F0 (H) Description Playback at 1/2 (1, 2) x speed Playback at 1 (2, 4) x speed Playback at 2 (4, 8) x speed Playback at 3 (6, 12) x speed Playback at 4 (8, 16) x speed Playback at 5 (10, 20) x speed Playback at 6 (12, 24) x speed Playback at 7 (14, 28) x speed Playback at 8 (16, 32) x speed VP0 to 7 = E0 (H) VP0 to 7 = C0 (H) VP0 to 7 = A0 (H) VP0 to 7 = 80 (H) VP0 to 7 = 60 (H) VP0 to 7 = 40 (H) VP0 to 7 = 20 (H) VP0 to 7 = 00 (H) Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Regarding the values in parentheses, the former ones are for when DSPB is 1 and VPCTL0, 1 = 0, and the latter ones are for when DSPB is 1, VPCTL0 = 1 and VPCTL1 = 0. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... - 57 - CXD3011R-1 $DX commands contin. 16 14 12 R - Relative velocity [Multiple] 10 8 DSPB = 1 6 4 DSPB0 = 0 2 E0 C0 A0 80 VP0 to 7 setting value [HEX] 60 40 20 00 When VPCTL0 = VPCTL1 = 0 32 28 24 R - Relative velocity [Multiple] 20 16 DSPB = 1 12 8 DSPB = 0 4 E0 C0 A0 80 VP0 to 7 setting value [HEX] 60 40 20 00 When VPCTL0 = 1, VPCTL1 = 0 - 58 - CXD3011R-1 $EX commands Command D3 SPD mode CM3 Data 1 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.1 Description Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA 1 See Timing Charts 1-6 to 1-12. Command bit EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 Mode INV VPCO 0 0 0 0 1 Description CLV-N Crystal reference CLV servo. CLV-W Used for playback in CLV-W mode.2 CAV-W Spindle control with VP0 to 7. CAV-W Spindle control with the external PWM. VCO-C VCO control3 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. 3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode. - 59 - CXD3011R-1 $EX commands contin. Mode DCLV DCLV PWM MD LPWR Command KICK 0 0 0 BRAKE STOP KICK CLV-N 1 1 0 0 0 BRAKE STOP KICK BRAKE STOP KICK 0 CLV-W 1 0 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 0 1 BRAKE STOP KICK BRAKE STOP Timing chart 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-11 (a) 1-11 (b) 1-11 (c) 1-12 (a) 1-12 (b) 1-12 (c) Mode CLV-N DCLV 1 DCLV PWM MD 0 1 0 LPWR 0 0 0 1 0 1 Timing chart 1-13 1-14 1-15 1-16 1-17 (EPWM = 0, FGON = 0) 1-18 (EPWM = 0, FGON = 0) 1-19 (EPWM = 1, FGON = 0) 1-20 (EPWM = 1, FGON = 0) CLV-W 1 CAV-W 1 0 0 1 Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 60 - CXD3011R-1 $EX commands contin. Command SPD mode Data 4 D3 Gain CAV1 D2 Gain CAV0 D1 FCSW D0 INV VPCO Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with VP7 to 0 in CAV-W mode. Note) Gain CAV1, 0 commands are not valid for spindle control with the external PWM. Command bit FCSW = 0 FCSW = 1 Processing The VPCO2 pin is not used and it is high impedance. The VPCO2 pin is used and the pin signal is the same as VPCO1. - 61 - Timing Chart 1-3 LRCK 48 bit slot WDCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG - 62 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits Lch C2 Pointer CXD3011R-1 Timing Chart 1-4 750ns to 120s 80 81 96 1 2 3 SQCK SQSO CRCF D0 15-bit peak-data Absolute value display, LSB first D1 D2 D3 D4 D5 D6 D13 D14 L/R Sub Q Data See "Sub Code Interface" Peak data L/R flag 2 3 1 2 3 - 63 - 96 clock pulses L/R CRCF 16 bit R/L Peak data of this section 1 WFCK 96 clock pulses SQCK SQSO CRCF 96 bit data Hold section Level Meter Timing CXD3011R-1 Timing Chart 1-5 1 1 2 2 3 3 WFCK 96 clock pulses 96 clock pulses SQCK - 64 - CRCF Measurement CRCF CRCF Measurement Measurement Peak Meter Timing CXD3011R-1 CXD3011R-1 Timing Chart 1-6 CLV-N mode DCLV = DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-7 CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z FSW L FSW L FSW L H MON MON H MON L (a) KICK (b) BRAKE (c) STOP - 65 - CXD3011R-1 Timing Chart 1-8 CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0 KICK H MDS MDS BRAKE STOP L MDS MDP H MDP L H MDP L L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-9 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). (b) BRAKE Other than when following the velocity, the timing is the same as Timing Chart 1-6 (b). (c) STOP - 66 - CXD3011R-1 Timing Chart 1-10 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). Timing Chart 1-11 CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP - 67 - CXD3011R-1 Timing Chart 1-12 CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP Timing Chart 1-13 CLV-N mode DCLV PWM MD = LPWR = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Z Deceleration Timing Chart 1-14 CLV-N mode DCLV PWM MD = 1, LPWR = 0 MDS Acceleration MDP 132kHz 7.6s Output Waveforms with DCLV = 1 n * 236 (ns) n = 0 to 31 Deceleration - 68 - CXD3011R-1 Timing Chart 1-15 CLV-W mode DCLV PWM MD = LPWR = 0 MDS Z Acceleration MDP Z Deceleration Output Waveforms with DCLV = 1 264kHz 3.8s Timing Chart 1-16 CLV-W mode DCLV PWM MD = 0, LPWR = 1 MDS Z Acceleration MDP Z 264kHz 3.8s Output Waveforms with DCLV = 1 The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-17 CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-18 CAV-W mode EPWM = DCLV PWM MD = 0, LPWR=1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 69 - CXD3011R-1 Timing Chart 1-19 CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-20 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 70 - CXD3011R-1 [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Sub-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register. * First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. * The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. * The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) * The high and low intervals for SQCK should be between 750ns and 120s. - 71 - CXD3011R-1 Timing Chart 2-1 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 72 - Block Diagram 2-2 (ASEC) 80 bit S/P Register (AMIN) ADDRS CTRL (AFRAM) SUBQ SIN ABCDE FGH 8 Order Inversion 8 8 8 8 8 8 8 8 HGFEDCBA 80 bit P/S Register SI SO LD LD LD LD LD LD LD SUBQ LD - 73 - CRCC Monostable multivibrator SHIFT LOAD CONTROL SO 16 bit P/S register SI 16 Peak detection ABS time load control for peak value SHIFT SQCK Ring control 1 Ring control 2 CRCF Mix SQSO CXD3011R-1 Timing Chart 2-3 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK SCOR Determined by mode CRCF1 80 or 96 Clock CRCF2 SQSO CRCF1 SQCK Register load forbidder - 74 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Monostable Multivibrator (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD3011R-1 Timing Chart 2-4 Example: $802000 latch Set SQCK high during this interval. XLAT 750ns or more Internal signal latch SQCK SQSO GFS LOCK EMPH ALOCK PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK VF1 VF2 VF3 VF4 VF5 VF0 VF6 VF7 VF8 VF9 Signal Description PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK. GFS High when the frame sync and the insertion protection timing match. LOCK GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. - 75 - Description C2F2 0 0 0 0 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 -- -- EMPH High when the playback disc has emphasis. ALOCK GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. VF0 to 9 Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. C1F2 C1F1 C1F0 Description No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset -- C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set 0 0 0 No C1 errors; C1 pointer reset 0 0 1 One C1 error corrected; C1 pointer reset 0 1 0 0 1 1 1 0 0 No C1 errors; C1 pointer set 1 0 1 One C1 error corrected; C1 pointer set 1 1 0 Two C1 errors corrected; C1 pointer set CXD3011R-1 1 1 1 C1 correction impossible; C1 pointer set CXD3011R-1 Timing Chart 2-5 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load VF0 to 9 m The relative velocity of the disc can be obtained with the following equation. R= (m + 1) (R: Relative velocity, m: Measurement results) 32 VF0 to 9 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 76 - Timing Chart 2-6 XLAT SQCK - 77 - 8 7 6 5 4 3 2 1 C1 error rate 7 3 5 0 0 7 SQSO C1 MSB 19 18 17 16 15 14 13 12 11 10 9 0 19 18 17 16 15 14 13 12 11 10 9 8 C2 error rate 7 6 5 4 3 2 1 0 0 3 5 0 CXD3011R-1 CXD3011R-1 [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control (however, variable pitch cannot be used). The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the VCKI pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode, set DCLV PWM MD to low. Note) The capture range for this mode is theoretically up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values, or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E665X command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to x32 speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity measurement is a signal of 132.3kHz obtained by dividing XTAL (XTLI, XTLO) (384Fs) by 128. The velocity is obtained by counting half of V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VF0 to 10). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to 7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode. - 78 - CXD3011R-1 3-4. VCO-C Mode This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to 7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation. 1 (256 - n) 32 n: VP0 to 7 setting value 1: VPCTL0, 1 setting value V16M = The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. * When DSPB = 0 VCO1 = V16M x * When DSPB = 1 VCO1 = V16M x 49 16 49 24 - 79 - CXD3011R-1 CAV-W Rotational velocity CLVS Target speed CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E6C00 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart - 80 - CXD3011R-1 VCO-C Mode Access START R? (How many minutes of absolute time?) What is the playback speed, when access ends? n? (Calculate n) Calculate VP0 to 7. Transfer $E00510 Switch to VCO control mode. EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer VP0 to 7. ( corresponds to VP0 to 7.) Transfer $DX XX Track Jump Subroutine Transfer $E66500 Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END Fig. 3-3. Access Flow Chart Using VCO Control - 81 - CXD3011R-1 [4] Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3011R-1 has a built-in three-stage PLL. * The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock. * The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes 50kHz. * A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. - 82 - CXD3011R-1 Block Diagram 4-1 CLV-W CAV-W Spindle rotation information Clock input 1/2 XTLI XTSL 1/32 Selector VPCO1 to 2 Phase comparator CLV-N 1/2 1/l 1/n CLV-W CAV-W /CLV-N l = 1, 2, 3, 4 (VPCTL0, 1) Microcomputer control 1/K (KSL1, 0) n = 1 to 256 (VP7 to 0) VCOSEL2 LPF VCTL VCO2 V16M 2/1 MUX VPON VCKI 1/M Phase comparator PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL VCOSEL1 - 83 - CXD3011R-1 4-2. Frame sync protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD3011R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 12, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 12 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. Default values. These values can be set as desired by $C commands SFP0 to 3 and SRP0 to 3. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD3011R-1 uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. * The correction status can be monitored externally. See Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible; C2 correction impossible; Table 4-2. - 84 - No C1 errors; One C1 error corrected; Two C1 errors corrected; C1 correction impossible; No C2 errors; One C2 error corrected; Two C2 errors corrected; Three C2 errors corrected; Four C2 errors corrected; -- C1 pointer copy C2 pointer set No C1 errors; One C1 error corrected; -- -- C1 pointer set C1 pointer set C1 pointer set C1 pointer set C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset Description C1 pointer reset C1 pointer reset CXD3011R-1 Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 4-4. DA Interface Output * The CXD3011R-1 has two DA interface output modes. a) 48-bit slot interface output This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface output This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. However, the DA output for the 64-bit slot supports 16x speed. - 85 - Timing Chart 4-4 48-bit slot Normal-Speed Playback PSSL = L LRCK (44.1K) 5 6 7 8 9 10 11 12 24 1 2 3 4 DA15 (2.12M) WDCK DA16 L14 L13 L12 L11 L10 L9 L8 L7 R0 Lch MSB (15) L6 L5 L4 L3 L2 L1 L0 Rch MSB - 86 - 24 L0 Rch MSB 48-bit slot Double-Speed Playback LRCK (88.2K) 12 DA15 (4.23M) WDCK DA16 R0 Lch MSB (15) CXD3011R-1 Timing Chart 4-5 64-bit slot Normal Speed PB PSSL = L DA12 (44.1K) 7 8 9 10 11 12 13 14 15 20 30 31 32 1 2 3 4 5 6 DA13 (2.82M) DA14 Rch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 Lch LSB (0) - 87 - 10 15 20 25 30 31 32 Rch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lch LSB 64-bit slot Double- Speed PB DA12 (88.2K) 1 2 3 4 5 DA13 (5.64M) DA14 L15 CXD3011R-1 CXD3011R-1 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3011R-1 supports type 2 form 1. This LSI supports 2 kinds of Digital Out generation methods; one is to generate the Digital Out using the PCM data read out from the disc and the other is to generate it using the DA interface input (PCMDI, LRCKI and BCKI). 4-5-1. Digital Out From PCM Data The Digital Out is generated from the PCM data which is read out from the disc. The clock accuracy of the channel status is automatically set to level II when the crystal clock is used and to level III in CAV-W mode. In addition, the Sub Q data matched twice continuously with CRC check are input to the initial 4 bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1. Therefore, DOUT is set to off by making MD2 pin to 0. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 bits0 to 3 Sub-Q control bits that matched twice with CRCOK bit29 VPON: 1 X'tal: 0 Table 4-6-1. - 88 - CXD3011R-1 4-5-2. Digital Out From DA Interface Input The Digital Out is generated from the DA interface. Validity Flag and User Data The Validity Flag and User Data are fixed to 0. Channel Status Data For the Channel Status Data, bits 0, 6 and 7 are fixed to 0. The following items can be set by bits 1, 2, 3 and 8. a) Digital data/audio data b) Digital copy enabled/ prohibited c) With/without pre-emphasis d) Category code (two types possible) Digital Out C bit 0 0 0 1 2 3 4 0 5 0 6 0 7 0 8 CAT b8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 A/D COPY EMPH D SEL En 0 0 0 16 0 0 0 0 0 0 0 0 0 0 0 0 32 48 0 176 Table 4-6-2. Note) In this method, DOUT can be set to off by making the MD pin to 0 and $34A command DOUT EN to 0. - 89 - CXD3011R-1 Digital Audio Data Input The input signal of the digital audio data is input from the DAC input pins PCMDI, LRCKI and BCKI. The input format supports 32-bit slot/LSB first, 64-bit slot/LSB first and 48-bit slot/MSB first. The input format can be selected by $34A command MLSL. DAC supports only 48-bit slot input. In MLSL=0, therefore, DAC should be forcibly muted. 1) MLSL = 0 32-bit slot/LSB first, 64-bit slot/LSB first (The DAC output requires the forcible muting.) 2) MLSL = 1 48-bit slot/MSB first (The DAC output is possible at the same time.) Mute Function By setting the command bit DOUT_DMUT to 1, all the audio data portions in the Digital Out output can be made to 0 with the Channel Status Data as it is. Input/Output Synchronization Circuit In the normal operation, the DAC automatically synchronizes with the input LRCK. However, when the input data has much jitter or the power is turned on the synchronization may not be achieved. In such a case, the internal operation should be forcibly synchronized by setting $34A DOUT WOD to 1. Also, the forcible synchronization is required when the operating frequency is changed such as switching between CLV and CAV,etc. Be sure to set DOUT WOD to 0 before performing forcible synchronization again. When the synchronization is performed, the internal counter which counts the frames is cleared so that the frame is started from 0 after the synchronization processed. In case where the automatic processing of the synchronization is not desirable or the user wants to do it manually, set the command $34A WIN EN to 0 to invalidate the automatic synchronization circuit. Clock System of DOUT Circuit For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the DAC block. Set MCSL to 1 for 768fs and to 0 for 384fs. - 90 - DOUT Block Input Timing Chart LRCKI (44.1k) (1) 32bit slot LSB first BCKI PCMDI L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 R0 - 91 - 7 10 17 18 8 9 L ch LSB (0) L1 L2 L3 L4 L5 L6 L7 (2) 64bit slot LSB first 1 2 3 4 5 6 BCKI PCMDI L8 L9 L10 L11 L12 L13 L14 L15 R ch LSB (0) (3) 48bit slot MSB first 5 6 10 7 8 9 1 2 3 4 BCKI PCMDI L ch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch MSB (15) CXD3011R-1 CXD3011R-1 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that does not accept commands from the CPU, that is $0, 1 and 2 commands. ($3 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-9. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. - 92 - CXD3011R-1 * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-11. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-12. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track jump count is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N - for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. * M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-13. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. - 93 - CXD3011R-1 Auto focus Focus search up FOK = H YES NO FZC = H YES NO Check whether FZC is continuously high for the period of time E set with register 5. FZC = L YES Focus servo ON NO END Fig. 4-8-(a). Auto Focus Flow Chart $47 Latch XLAT FOK FZC BUSY Command for SSP $03 Blind E $08 Fig. 4-8-(b). Auto Focus Timing Chart - 94 - CXD3011R-1 1 Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) COUT = YES Track REV kick WAIT (Brake B) Track, sled servo ON NO (FWD kick for REV jump) END Fig. 4-9-(a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 4-9-(b). 1-Track Jump Timing Chart - 95 - CXD3011R-1 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT x 5) COUT = 5 ? YES Track, REV kick NO C = Overflow ? YES Track, sled servo ON Checks whether the COUT cycle is longer than overflow C. NO END Fig. 4-10-(a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A Command for SSP COUT 5 count Overflow C $2A ($2F) $2E ($2B) $25 Fig. 4-10-(b). 10-Track Jump Timing Chart - 96 - CXD3011R-1 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N NO Counts COUT for the first 16 times and MIRR for more times. YES Track REV kick C = Overflow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 4-11-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for SSP $2A ($2F) COUT (MIRR) N count $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 4-11-(b). 2N-Track Jump Timing Chart - 97 - CXD3011R-1 Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N? YES NO Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-12-(a). Fine Search Flow Chart $44 (REV = $45) latch XLAT COUT BUSY Kick D $26 ($27) Kick F Traverse Speed Control (Overflow G) & COUT N count Kick D $27 ($26) $25 $2A ($2F) Fig. 4-12-(b). Fine Search Timing Chart - 98 - CXD3011R-1 M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) COUT (MIRR) = M Counts COUT for M < 16. Counts MIRR for M 16. NO YES Track, Sled Servo OFF END Fig. 4-13-(a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for servo $22 ($23) COUT (MIRR) M count $20 Fig. 4-13-(b). M-Track Move Timing Chart - 99 - CXD3011R-1 4-7. Digital CLV Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 Mux Gain MDS Gain DCLV CLV P/S Over Sampling Filter-2 Noise Shape KICK, BRAKE, STOP Modulation PWMI DCLVMD, LPWR Mode Select MDS CLVS U/D: MDS error: MDP error: PWMI: MDP Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-14. Block Diagram - 100 - CXD3011R-1 4-8. Playback Speed In the CXD3011R, the following playback modes can be selected through different combinations of XTLI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. VCOSEL11 0/1 0/1 1 1 0/1 0/1 0/1 Playback speed 1x 2x 2x 4x 1x 2x 1x Mode 1 2 3 4 5 6 7 XTLI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 1 ASHS 0 0 1 1 0 0 0 Error correction C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. The playback speed can be varied by setting VP0 to 7 in CAV-W mode. See "[3] Description of Modes" for details. - 101 - CXD3011R-1 4-9. DAC Block Playback Speed The operating speed of the DAC block is determined by the crystal and the $AX command MCSL regardless of the operating conditions of the CD-DSP block. This allows the DAC block and DSP block playback modes to be set independently. 1-bit DAC block playback speed X'tal 768Fs 768Fs 384Fs MCSL 1 0 0 DAC block playback speed 1x 2x 1x Fs = 44.1kHz 4-10. DAC Block Input Timing The DAC input timing chart is shown below. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3011R. This enables to send data to the DAC block via the external audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI. (See the Application Circuit.) Nomal-speed Playback LRCKI (44.1k) 1 BCKI (2.12M) PCMDI Invalid L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 - 102 - CXD3011R-1 Description of DAC Block Functions Zero data detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUTO and RMUTO pins go active when any one of the following conditions is met. The polarity can be selected by the $9X command ZDPL. * When zero data is detected * When the $9X commands DAC SMUTL and DAC SMUTR are set (The flags change independently for the left and right channels.) The mute flag output at initializing is as shown below. (This is in the case the zero data is input from LRCKI, BCKI, PCMDI and the time address $9X command ZDPL and address $AX command MCSL stay in the initial values.) XRST LMUTO RMUTO Approx. 370ms when crystal = 16.9344MHz Approx. 185ms when crystal = 33.8688MHz Attenuation operation Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches Y2. And, when the command X3 is sent before the audio output rteaches Y2 (B or C in the figure), the audio output approaches Y3 from the value (B or C in the figure) at that point. 0dB 400(H) A Y1 B Y3 C Y2 - 000(H) 23.2 [ms] - 103 - CXD3011R-1 DAC block mute operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. * When attenuation data of 000 (Hex) is set * When the $9X commands DAC SMUTL and DAC SMUTR are set to 1 Soft mute off 0dB Soft mute on Soft mute off - dB 23.2 [ms] 23.2 [ms] Forced mute Forced mute results when the $AX command FMUT is set to 1. Forced mute fixes the PWM output. (Low for left channel, high for right channel) Zero detection mute Setting $9X command ZMUT to 1 enables forced mute, when zero data is detected for both the left and right channels. (See "Zero data detection".) LRCK Synchronization Synchronization is performed at the first rising edge of the LRCK input when reset. After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. * When the XTSL pin switches between high and low * When the $9X command DSPB setting changes * When the $9X command MCSL setting changes * When operation switches between CLV mode and CAV mode LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in these cases as well. For resynchronization, set the $9X command XWOC to 0 or the external pin XWO to low, wait for one LRCK cycle or more, and then set XWOC to 1 and XWO to high. When setting XWOC to 0 or the external pin XWO to low, be sure to set the $9X command SYCOF to 0 beforehand. - 104 - CXD3011R-1 SYCOF When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores the LRCK's asynchronization, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI input. Set SYCOF to 0 other than when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode. Digital Bass Boost Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: MID and MAX. The bass boost is set using BSBST and BBSL of address A. See Graph 4-15 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 Normal DBB MID DBB MAX [dB] -2.00 -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 10 30 100 300 1k 3k 10k 30k Digital bass boost frequency response [Hz] Graph 4-15. - 105 - CXD3011R-1 4-11. Asymmetry Compensation Fig. 4-16 shows the block diagram and circuit example. CXD3011R ASYE ASYO R1 RFAC R1 R2 R1 ASYI R1 BIAS R1 2 = R2 5 Fig. 4-16. Asymmetry Compensation Application Circuit - 106 - CXD3011R-1 4-12. Clock System The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below. During normal use, the servo block clock is internally connected and the FSTIO pin is the monitor output pin. The command ($8 FSTIN) is used to input the clock externally. In this time, the FSTIO pin serves as the input pin. XTLI 384fs or 768fs XTLO OSC To DAC block MCKO To exterior 1/2 XTSL To CD signal processor block 2/3 FSTIO FSTIN = 0: Output pin (Preset) FSTIN = 1: Input pin FSTIN (Command $8X. "0" for preset; internally connected) 1/2 To digital servo block Selector 1/4 XT1D XT2D XT4D (Command $3E, $3F) - 107 - CXD3011R-1 [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 8-bit DAC Offset cancel Focus bias adjustment Focus search Gain-down Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 8-bit DAC Offset cancel E:F balance adjustment Track jump Gain-up Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Other: 345Hz (when MCK = 128Fs) 1/4VDD to 3/4VDD 8-bit DAC Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement - 108 - CXD3011R-1 5-2. Digital Servo Block Master Clock (MCK) The FSTIO pin is the clock input/output pin for the servo block. At preset, the clock with 2/3 frequency of the crystal is internally supplied to the servo block and the FSTIO pin serves as the monitor output pin for it. To make this pin act as the input pin, set the command $8X command FSTIN to 1. The master clock (MCK) is generated by dividing the frequency of the FSTIO pin. The frequency division ratio is 1, 1/2 or 1/4. Table 5-1 below assumes the preset status (where the clock with 2/3 frequency of the crystal is internally supplied to the servo). XT4D and XT2D are for the $3F command and XT1D is for the $3E command. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 1 2 3 4 5 6 7 XTLI 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO (FSTI) 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL 0 1 XT4D 0 1 0 XT2D 1 0 1 0 0 XT1D 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 5-1. - 109 - CXD3011R-1 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3011R-1 can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3011R, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are VCLM, FLM, RFLM and TLM of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (Hex). XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s AVRG measurement completed Timing Chart 5-2. CXD3011R-1 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT1, SOCT0. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to 1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes to high and the counter stop can be monitored. A FBIAS setting value (FB9 to 1) B C LIMIT value (FBL9 to 1) Here, assume the FBIAS setting value FB9 to 1 and the FBIAS LIMIT value FBL9 to 1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 x VDD/2. A: Register mode B: Counter mode C: Counter mode (when stopped) SENS pin - 111 - CXD3011R-1 RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC1 * TLD1 TLC2 * TLD2 - to SLD In register TE from A/D - - to TRK In register TE AVRG register TLC1 TRVSC register TLC2 FE from A/D FE AVRG register - FLC1 FBIAS register + FBON to FCS In register FLC0 - to FZC register Fig. 5-3a. RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC0 * TLD0 TLC2 * TLD2 - to SLD In register TE from A/D - TLC0 VC AVRG register TRVSC register TLC2 - to TRK In register VCLC FE from A/D FE AVRG register - + FLC0 FBIAS register FBON to FCS In register - to FZC register Fig. 5-3b. - 112 - CXD3011R-1 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 5-4 Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 113 - CXD3011R-1 AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3011R-1 confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL start SENS AGJ AGCNTL completion Fig. 5-5. Note) Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller value. - 114 - CXD3011R-1 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 115 - CXD3011R-1 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 0010 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3011R-1 has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x, or 4x magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) 3 SELECT 0011 0001 0010 0011 Table 5-10. - 116 - CXD3011R-1 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold -Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 -Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. - 117 - CXD3011R-1 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 5-13. 5-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK DAC TRK Gain Normal Filter Fig. 5-14. - 118 - CXD3011R-1 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B) Inner track Outer track FWD REV Servo ON JMP JMP TRK DRV TRK DRV Outer track Inner track REV FWD Servo ON JMP JMP RF Trace MIRR TE 0 RF Trace MIRR TE 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 0 0 Fig. 5-15. Register name Fig. 5-16. Command D23 to D20 D19 to D16 10 0 1 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Table 5-17. - 119 - 1 TRACKING CONTROL 0001 CXD3011R-1 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) * DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result XLAT tDLS $3953: $3963: $391C: $391D: FCS AGCNTL coefficient result TRK AGCNTL coefficient result TRVSC adjustment result FBIAS register value tSPW SCLK 1/fSCLK Serial Readout Data (SENS pin) ... MSB ... LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 Unit MHz ns s tSPW tDLS 31.3 15 Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). - 120 - CXD3011R-1 5-15. Writing to the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. - 121 - CXD3011R-1 5-16. DAC Output FCS, TRK and SLD DAC format outputs are described below. See the "Servo Drive Analog Characteristics" of Electrical Characteristics for the output range. In particular, FSC and TRK use a double oversampling noise shaper. Timing Chart 5-22 and Fig. 5-23 show examples of output waveforms and drive circuits. Output value +B SLD 64MCK VDD 0.9VDD B VDD 256 Output value -B 64MCK Output value 0 64MCK SAO 0.5VDD -B VDD 128 0.1VDD 0 FCS/TRK VDD 0.9VDD 32MCK 32MCK 32MCK 32MCK 32MCK 32MCK 0.5VDD FAO/TAO 0.1VDD 0 B VDD 256 B VDD 256 -B VDD 256 -B VDD 256 Timing Chart 5-22. VCC R R VDD/2 AO R R DRV Fig. 5-23. Drive Circuit - 122 - CXD3011R-1 5-17. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. - 123 - CXD3011R-1 5-18. Description of Commands and Data Sets $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 0 D0 0 PGFS1 PGFS0 PFOK1 PFOK0 MRT2 MRT1 These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed. PGFS1 0 0 1 1 PGFS0 0 1 0 1 Processing High when the frame sync is of the correct timing, low when not the correct timing. High when the frame sync is of the correct timing, low when continuously not the correct timing for 2ms or longer. High when the frame sync is of the correct timing, low when continuously not the correct timing for 4ms or longer. High when the frame sync is the correct timing, low when continuously not the correct timing for 8ms or longer. These commands set the FOK hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. PFOK1 0 0 1 1 PFOK0 0 1 0 1 Processing High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. These commands limit the time while Mirr = high. These are the values when MCK = 128Fs, and the time limit is inversely proportional to the MCK setting. MRT2 0 0 1 1 MRT1 0 1 0 1 Time limit No time limit 1.1ms 2.2ms 4.0ms - 124 - CXD3011R-1 $34A (preset: $34A 150) D15 1 D14 0 D13 1 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT SEL EN D b8 EN DMUT WOD EN MLSL Command bit A/DSEL = 0 A/DSEL = 1 Processing Channel status data. Bit 1 is output as the audio data. Channel status data. Bit 1 is output as the data other than the audio data. Command bit COPY EN = 0 COPY EN = 1 Processing Channel status data. Bit 2 is output as the digital copy prohibited. Channel status data. Bit 2 is output as the digital copy enabled. Command bit EMPH D = 0 EMPH D = 1 Processing Channel status data. Bit 3 is output without pre-emphasis. Channel status data. Bit 3 is output with pre-emphasis. Command bit CAT b8 = 0 CAT b8 = 1 : Preset Command bit DOUT EN = 0 DOUT EN = 1 Processing Channel status data. Bit 8 is output as 0. Channel status data. Bit 8 is output as 1. Processing DOUT signal, which is generated from PCM data read out from the disc, is output. DOUT signal, which is generated from the DA interface input, is output. Command bit DOUT DMUT = 0 DOUT DMUT = 1 Command bit DOUT WOD = 0 DOUT WOD = 1 Processing Digital Out output is normally output. All the audio data portions are output in 0, with Digital Out output as it is. Processing DOUT sync window is not open. DOUT sync window is open. - 125 - CXD3011R-1 $34A commands contin. Command bit WIN EN = 0 WIN EN = 1 Processing The operation is invalidated, where the input LRCK is automatically synchronized with the internal processing to match the phase. The operation is validated, where the input LRCK is automatically synchronized with the internal processing to match the phase. Command bit DOUT EN2 = 0 DOUT EN2 = 1 Processing Digital Out is not generated from the DA interface input. Select when Digital Out is generated from the DA interface input. Note) In order to generate Digital Out from the DA interface, set DOUT EN to 1 and EN2 to 1. : Preset DOUT EN 0 0 0 0 0 0 0 0 0 1 DOUT DMUT -- -- -- -- -- -- -- -- -- 0 MD2 pin 0 1 1 1 1 1 1 1 1 -- Other mute condition -- 0 0 0 0 1 1 1 1 -- DOUT Mute -- 0 0 1 1 0 0 1 1 -- D. out Mute F -- 0 1 0 1 0 1 0 1 -- DOUT output OFF 0dB The output from the PCM data readout from a disc - dB The output from the PCM data readout from a disc 0dB The output from the DA interface input - dB The output from the DA interface input --: don't care 1 1 -- -- -- -- See the "Mute conditions" (1), (2) and (4) to (6) of $AX commands for the other mute conditions. See $8X commands for DOUT Mute and D. out Mute F. - 126 - CXD3011R-1 $34B (preset: $34B 000) D15 1 D14 0 D13 1 D12 1 D11 D10 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFBK1 SFBK2 The low frequency can be boosted for brake operation. See 5-12 for brake operation. SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. The preset is 0. - 127 - CXD3011R-1 $34C (preset: $34C 000) D15 1 D14 1 D13 0 D12 0 D11 THB ON D10 FHB ON D9 D8 D7 D6 0 D5 D4 D3 D2 D1 D0 TLB1 FLB1 TLB2 ON ON ON HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 These commands turn on the boost function. (See " 5-20. Filter Composition".) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: When 1, the high frequency is boosted for the TRK filter. Preset when 0. FHBON: When 1, the high frequency is boosted for the FCS filter. Preset when 0. TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset when 0. TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK jump operation. The following commands set the boosters. (See " 5-20. Filter Composition".) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-24a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.) An example of characteristics is shown in Fig. 5-26a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.) An example of characteristics is shown in Fig. 5-26b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.) An example of characteristics is shown in Fig. 5-26c. This booster is used exclusively with the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK jump operation. Note) Fs = 44.1kHz - 128 - CXD3011R-1 BK3 Z-1 BK1 BK2 Z-1 HighBooster setting HBST1 0 1 1 HBST0 -- 0 1 BK1 -120/128 -124/128 -126/128 BK2 96/128 112/128 120/128 BK3 2 2 2 Fig. 5-24a. Table 5-25a. BK6 Z-1 BK4 BK5 Z-1 LB1S1 0 1 1 LB1S0 BK4 -- 0 1 LowBooster-1 setting BK5 1023/1024 2047/2048 4095/4096 BK6 1/4 1/4 1/4 -255/256 -511/512 -1023/1024 Fig. 5-24b. Table 5-25b. BK9 Z-1 BK7 BK8 Z-1 LB2S1 0 1 1 LB2S0 BK7 -- 0 1 LowBooster-2 setting BK8 1023/1024 2047/2048 4095/4096 BK9 1/4 1/4 1/4 -255/256 -511/512 -1023/1024 Fig. 5-24c. Table 5-25c. - 129 - CXD3011R-1 15 12 9 3 6 3 2 1 Gain [dB] 0 -3 -6 -9 -12 -15 1 10 100 Frequency [Hz] 1k 10k +90 +72 3 2 1 +36 Phase [degree] 0 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) 1 HBST1 = 0 2 HBST1 = 1, HBST0 = 0 - 130 - 3 HBST1 = 1, HBST0 = 1 CXD3011R-1 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26b. Servo LowBooster1 characteristics [FCS, TRK] (MCK = 128Fs) 1 LB1S1 = 0 2 LB1S1 = 1, LB1S0 = 0 - 131 - 3 LB1S1 = 1, LB1S0 = 1 CXD3011R-1 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26c. Servo LowBooster2 characteristics [FCS, TRK] (MCK = 128Fs) 1 LB2S1 = 0 2 LB2S1 = 1, LB2S0 = 0 - 132 - 3 LB2S1 = 1, LB2S0 = 1 CXD3011R-1 $34D (preset: $34D 000) D15 1 D14 1 D13 0 D12 1 D11 D10 D9 D8 0 D7 D6 D5 D4 0 D3 0 D2 0 D1 0 D0 0 FAON TAON SAON FAOZ TAOZ SAOZ The servo drive is output. DAC format. FAON: When 0, the FCS servo drive is muted. (default) When 1, the FCS servo drive is output. TAON: When 0, the TRK servo drive is muted. (default) When 1, the TRK servo drive is output. SAON: When 0, the SLD servo drive is muted. (default) When 1, the SLD servo drive is output. These commands select the drive DAC output when the servo is off. Center voltage or high impedance can be selected. FAOZ: When 0, the FCS drive DAC output is the center voltage when the FCS servo is off. (default) When 1, the FCS drive DAC output is high impedance when the FCS servo is off. TAOZ: When 0, the TRK drive DAC output is the center voltage when the TRK servo is off. (default) When 1, the TRK drive DAC output is high impedance when the TRK servo is off. Set SFJP ($36) to 1 or TAOZ to 0 in order to boost the low frequency for the TRK Jump operation by the $34C command TLB2ON. SAOZ: When 0, the SLD drive DAC output is the center voltage when the SLD servo is off. (default) When 1, the SLD drive DAC output is high impedance when the SLD servo is off. - 133 - CXD3011R-1 $34F D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write two's complement data, FB9 = MSB. FB9 to FB1: Data; For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/4 and FB9 to FB1 = 100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/4 and TV9 to TV0 = 1100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) Note) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bits TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 134 - CXD3011R-1 $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDD V/s) FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage FS5 to Fs0: Focus search limit voltage Default value: 011000 ((1 24/64) x VDD/2, VDD: supply voltage) Focus drive output conversion AGF convergence gain setting value Default value: 0101101 FG6 to FG0: $36 (preset: $36 0E 2E) D15 D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 TDZC DTZC TJ5 TDZC: TJ0 SFJP TG6 DTZC: TJ5 to TJ0: SFJP: TG6 to TG0: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. When TDZC = 0, the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. When TDZC = 1, the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross, whichever has the fastest phase, is used. (See 4-3.) DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) Track jump voltage Default value: 001110 ((1 14/64) x VDD/2, VDD: supply voltage) Surf jump mode on/off The tracking drive output is generated by adding the tracking filter output and TJReg (TJ5 to 0), by setting SFJP to 1. Set SFJP to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump operation by the $34C command TLB2ON. AGT convergence gain setting value Default value: 0101110 - 135 - CXD3011R-1 $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD/2, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD/2 1/8 x VDD/2 1/16 x VDD/2 1/32 x VDD/2 : preset SM5 to SM0: AGS: AGJ: Sled move voltage Default value: 010000 ((1 16/64) x VDD/2, VDD: supply voltage) AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1/32 x VDD/2 1 (large) 1/16 x VDD/2 0 (small) 1/16 x VDD/2 1 (large) 1/8 x VDD/2 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) AGGF: AGGT: - 136 - CXD3011R-1 $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1. - 137 - CXD3011R-1 $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: SD6 to SD0: SD6 1 0 Serial data readout DAC mode (on/off) Serial readout data select SD5 Readout data Readout data length 8 bits 16 bits Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 SD3 to SD0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) - (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits $399F $399E $399D $399C $3993 $3992 $3991 $398C $3988 $3984 $3983 $3982 $3981 $3980 : Don't care 0 Note) Coefficients K40 to K4F cannot be read out. See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data. - 138 - CXD3011R-1 $3A (preset: $3A 00 00) D15 0 FBON: D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 0 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 SJHD INBK MTI0 FBSS: FBUP: FBV1, FBV0: FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting FBON = 1 (on). FBIAS (focus bias) register/counter switching FBSS = 0: register, FBSS = 1: counter. FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter. FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. FBV1 FBV0 0 1 0 1 Number of steps per cycle 1 2 4 8 : preset The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 x VDD/2, VDD = supply voltage. 0 0 1 1 TJD0: FPS1, FPS0: TPS1, TPS0: This sets the tracking servo filter to 0 when switched from track jump to servo on even if SFJP = 1 (during surf jump operation). Gain setting for the whole focus filter. Gain setting for the whole tracking filter. These are effective for increasing the overall gain in order to widen the servo band. (See " 5-20. Filter Composition".) FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SJHD: INBK: MTI0: This holds the tracking filter output at the value when surf jump starts during surf jump. The masking method for the brake circuit is selected. When INBK = 1, the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1. - 139 - CXD3011R-1 $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD/2, VDD: supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 x VDD/2 20/256 x VDD/2 24/256 x VDD/2 28/256 x VDD/2 32/256 x VDD/2 40/256 x VDD/2 48/256 x VDD/2 56/256 x VDD/2 : preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDD V) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 0.0156 x VDD 0.0234 x VDD 0.0313 x VDD 0.0391 x VDD : preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time Default value: 00 (no timer limit) MAX2 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when 1. - 140 - CXD3011R-1 D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed [V/ms] 0 0 1 1 0 1 0 1 0.0431 x VDD 0.0861 x VDD 0.172 x VDD 0.344 x VDD [kHz] 22.05 44.1 88.2 176.4 D2V2 D2V1 : preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed [V/ms] 0 0 1 1 0 1 0 1 0.344 x VDD 0.688 x VDD 1.38 x VDD 2.75 x VDD [kHz] 176.4 352.8 705.6 1411.2 D1V2 D1V1 : preset, VDD: supply voltage RINT: This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. - 141 - CXD3011R-1 $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: These select the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin. When 0, the signal input to the TE pin is input to the TRK servo filter. When 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT : preset, --: don't care MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit. BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. This is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. BTS1 BTS0 0 0 1 1 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 - 142 - MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [s] 5.669 11.338 22.675 45.351 : preset (when MCK = 128Fs) CXD3011R-1 $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK SFID: TLD2 TLD1 TLD0 SFSK: THID: THSK: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low-frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as the TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. See " 5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands. TLD0 to 2: This turns on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to 2) and Fig. 5-3. Traverse center correction TLC2 0 1 TLD2 -- 0 1 TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 TLD1 -- 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON - 143 - SLD filter OFF ON OFF : preset, --: don't care CXD3011R-1 * Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, CXD3011R-1 outputs servo drives which are reversed phase of input errors. Negative input coefficient TE K19 TRK Filter Positive output coefficient K22 Negative input coefficient SE K00 SLD Filter Positive output coefficient K05 Positive input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient (K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0h results in 60h.) For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted. Negative input coefficient TE K19 TRK Filter MOD Positive output coefficient K22 Positive input coefficient SE K00 SLD Filter Positive output coefficient K05 Negative input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 for TRK servo gain normal See " 5-20. Filter Composition". - 144 - CXD3011R-1 $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default is 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1; default is 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See " 5-20 Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) TLCD: This command masks the TLC2 command of $38 only when FOK is low. On when 1; default when 0 LKIN: When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. COIN: When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care XT1D: The clock of the FSTIO pin is used without being frequency-divided as the master clock for the servo block by setting XT1D to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 145 - CXD3011R-1 $3F (preset: $3F 00 00) D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 D2 D1 D0 0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ LPAS SRO1 SRO0 AGHF This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. Sine wave amplitude AGG4 AGGF AGGT 0 0 1 -- -- 0 1 0 1 1 -- -- 0 1 0 1 0 1 FE input conversion 1/36 x VDD/2 1/16 x VDD/2 -- -- TE input conversion -- -- 1/16 x VDD/2 1/8 x VDD/2 1/64 x VDD/2 1/32 x VDD/2 1/16 x VDD/2 1/8 x VDD/2 See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. : preset, --: don't care XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated from the FSTIO pin clock. See the description of $3E for XT1D. And see " 4-12. Clock System". XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when 1; default when 0 FTQ: The focus search-up speed is set to the 1/4 value of that determined by FT1, FT0 and FTZ ($35). On when 1; default when 0 - 146 - CXD3011R-1 Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when 1; default when 0 Note) When using this mode, first check whether each error signal is properly A/D converted using the $3F commands SRO1 and SRO0. SRO1, SRO0: These commands are used to continuously externally output various data inside the digital servo block which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting these commands to 1 respectively. The default is 0, 0. (no readout) The output pins for each case are shown below. SRO1 = 1 SOCK XOLT SOUT DA13 pin DA12 pin DA14 pin SRO0 = 1 DA10 pin DA09 pin DA11 pin LPAS: (See "Description of Data Readout" on the following page.) AGHF: FTQ: This halves the frequency of the internally generated sine wave during AGC. The slope of the output during focus search is 1/4 of the conventional output slope. On when 1; default when 0 . - 147 - CXD3011R-1 Description of Data Readout SOCK (5.6448MHz) ... ... ... ... XOLT (88.2kHz) SOUT MSB ... LSB MSB ... LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * * To the 7-segment LED MSB SOCK CLK CLK Data is connected to the 7-segment LED by 4bits at a time. This enables Hex display using four 7-segment LEDs. XOLT MSB SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 148 - CXD3011R-1 5-19. List of Servo Filter Coefficients Fix indicates that normal preset values should be used. - 149 - CXD3011R-1 - 150 - 5-20. Filter Composition The internal filter composition is shown below. K: Coefficient RAM address, M: Data RAM address FCS Servo Gain Normal fs = 88.2kHz K0F M03 M05 M06 K11 K13 Z-1 K10 M07 Z-1 K0C 2-7 K0B Note) Set the MSB bit of the K0B and K0D coefficients to 0. K0D 2-7 27 K0E Z-1 K08 K09 K0A Z-1 M04 FCS Hold Reg 1 FCS AUTO Gain FCS Hold Reg2 DFCT FCS In Reg 2-1 K06 AGFON Sin ROM K06 FCS Servo Gain Down fs = 88.2kHz K28 M03 M05 Z-1 K26 2-7 K27 K29 2-7 K28 K2A Z-1 K24 K25 Z-1 M04 M06 K2D Z-1 K2C FCS Hold Reg 1 FSC AUTO Gain M07 K13 FCS Hold Reg2 DFCT - 151 - Note) Set the MSB bit of the K27 and K29 coefficients to 0. FPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 FCS In Reg 2-1 K06 DAC Z-1 FCS SRCH BK5 CXD3011R-1 TRK Servo Gain Normal fs = 88.2kHz To SLD Servo TRK Hold M0B M0D M0E K22 K23 Z-1 K21 M0F Z-1 K1E 2-7 2 K1F K1D Note) Set the MSB bit of the K1D and K1F coefficients to 0. -7 TRK Hold Reg M0C Z K1B K20 K1C -1 DFCT TRK AUTO Gain TRK In Reg Z-1 K1A 2-1 K19 AGTON Sin ROM K19 TRK Servo Gain Up 1 fs = 88.2kHz TRK AUTO Gain M0B M0E K3E M0F K23 Z-1 K3D Z-1 K1A K1B K3C Z-1 M0C 27 TRK Hold Reg DFCT TRK In Reg 2-1 K19 - 152 - M0B M0D Z-1 K38 K3A 2 2 K3B K39 -7 -7 TRK Servo Gain Up 2 fs = 88.2kHz TRK AUTO Gain M0C Z-1 K36 K37 K3C M0E Z-1 K3D K3E M0F K23 TRK Hold Reg DFCT TRK In Reg Z-1 2-1 K19 Note) Set the MSB bit of the K39 and K3B coefficients to 0. TPS1, 0 BK3 Z BK1 -1 BK6 BK9 Z-1 BK4 Z-1 TRK JMP BK5 Z -1 DAC Z-1 Z-1 BK2 BK7 BK8 CXD3011R-1 Note) Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump operation. FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3EAXX0) K0F M03 M05 K11 K13 Z-1 K0C 2-7 2 K0D K0E 27 K09 K0B -7 FCS Hold Reg 2 M04 Z-1 7FH K0A K10 2-7 2-7 K08 2-7 80H Z-1 M06 M07 DFCT FCS Hold Reg 1 FCS AUTO Gain FCS In Reg Z-1 81H 2-1 K06 AGFON Sin ROM K06 Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3E5XX0) K2B M03 M05 M06 K2D Z-1 K2C 2-7 K29 K2A Z-1 K28 2-7 K25 K27 2-7 80H Z-1 Z-1 7FH K26 2-7 K24 2-7 81H M04 M07 FCS Hold Reg 1 FCS AUTO Gain K13 FCS Hold Reg 2 DFCT FCS In Reg 2-1 K06 - 153 - FPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. DAC Z-1 FCS SRCH BK5 CXD3011R-1 TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3EXAX0) TRK AUTO Gain M0C M0D M0E K22 K23 Z-1 K21 2-7 K1F K20 M0F Z-1 K1E 2-7 K1B K1D 2-7 80H Z-1 7FH K1C 2-7 2-7 TRK Hold Reg DFCT TRK In Reg 2-1 M0B K19 AGTON Z-1 Sin ROM K19 81H K1A Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo Gain Up1; fs = 88.2kHz, during quasi double accuracy (Ex. $3EX5X0) TRK AUTO Gain M0C K3E M0F K23 Z-1 7FH K3D 2-7 K1B K3C 2-7 2-7 80H Z-1 M0E 27 TRK Hold Reg DFCT TRK In Reg 2-1 K19 M0B Z-1 81H K1A Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. - 154 - M0C M0D M0E Z-1 K3D 2-7 K3B K3C Z-1 K38 2-7 K37 K39 2-7 K3A 80H Z-1 7FH 2-7 2-7 K3E M0F K23 TPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 TRK Servo Gain Up2; fs = 88.2kHz, during quasi double accuracy (Ex. $3EX5X0) TRK AUTO Gain TRK Hold Reg DFCT TRK In Reg 2-1 K19 M0B Z-1 81H K36 Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. BK9 Z-1 TRK JMP BK5 BK7 BK8 Z-1 Z-1 DAC CXD3011R-1 Note) Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump operation. CXD3011R-1 SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D 2-1 SFID K00 Z-1 K01 2-7 K02 2-7 K04 Z-1 SLD MOV K03 SFSK (only when TGUP2 is used) M00 SLD In Reg M01 K05 TRK AUTO Gain M02 2-7 K07 DAC Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 155 - CXD3011R-1 Anti Shock fs = 88.2kHz 2-1 TRK In Reg K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2-1 SLD In Reg THID K40 Z-1 K41 2-7 K42 2-7 K44 Z-1 K43 THSK (only when TGUP2 is used.) M18 M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS Hold Reg 1 K48 M10 Z-1 K49 2-7 K4A 2-7 M11 Z-1 K4B K4D FCS Hold Reg 2 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 156 - CXD3011R-1 5-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 180 G - Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. FOCUS frequency response 40 NORMAL GAINDOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. - 157 - - Phase [degree] G - Gain [dB] - Phase [degree] GFS FOK XLAT XRST SCLK CLOK SENS MUTE SQCK SCOR SQSO DATA LDON XWO LPF Circuit FSW DFCT MIRR COUT LPF Circuit 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC NC NC NC FOK NC FSW XTLI MIRR XLAT ATSK DFCT DATA TESO CLOK SCLK COUT SENS AVSS3 XTLO AVDD4 AVSS4 AVSS5 DVSS4 DVDD4 AVDD3 AVDD5 DVSS3 XWO NC LMUTO PWMLN PWMLP PWMRP PWMRN RMUTO 109 NC NC 72 XRST 71 SCSY 70 SQCK 69 SQSO 68 EXCK 67 EXCK SBSO SBSO 66 SCOR 65 WFCK 64 WFCK MUTE 63 DOUT 62 MD2 61 DVDD3 60 C16M 59 C4M 58 FSTIO 57 NC 56 NC 55 NC 54 NC 53 MCKO 52 XTSL 51 DVSS2 50 DA01 49 DA02 48 DA03 47 DA04 46 DA05 45 DA06 44 DVDD2 43 DA07 42 DA08 41 DA09 40 DA10 39 DA11 38 NC 37 NC WDCK NC PSSL NC ASYE PCMDI DA15 BCKI AVDD1 DVSS1 DA16 DVDD1 LRCKI NC LRCK DA14 DA13 DA12 NC BIAS XPLCK XUGF GTOP RFCK XRAOF C2PO MCKO C16M C4M DOUT 110 AVSS6 111 SAO 112 TAO 113 FAO 114 BSSD AVDD6 115 116 MON 117 MDP 118 MDS LOCK 119 120 SSTP 121 DVSS5 122 DTS0 123 TES2 124 TES3 NC 125 126 NC 127 NC 128 129 PWMI 130 DVDD5 131 VCOO 132 VCOI 133 TEST 134 PDO 135 VCKI 136 V16M 137 AVDD2 IGEN 138 139 AVSS2 140 ADIO 141 RFDC CE 142 143 TE 144 NC NC VCTL VPCO1 VC PCO CLTV AVSS1 RFAC FE FILI SE FILO ASYI ASYO VPCO2 NC SSTP SLED Driver Circuit MON SPDL Driver Circuit FG MDS LOCK MNT0 MNT1 MNT2 MNT3 GND PDO ADIO TD FD LDON VCC GND 1 2 3 7 4 8 5 6 CE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TE FE VC SOUT WDCK SOCK XOLT RFO CXD3011R-1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. SCSY [6] Application Circuit - 158 - CXD3011R-1 Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 1.4 0.1 72 B A 144 37 1 0.5 36 0.22 0.05 0.08 M S S 0.1 S 0.1 0.05 0.22 0.05 (21.0) 0 to 10 DETAIL A 0.5 0.15 0.145 0.03 (0.2) (0.125) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.3 g SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.22 0.05 36 0.1 M S S 0.1 S 37 (21.0) 0.1 0.05 0.22 0.05 (0.125) (0.2) 0 to 10 DETAIL A 0.5 0.15 DETAIL B 0.145 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L022 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 1.3g - 159 - CXD3011R-1 Package Outline Unit: mm 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 0.1 72 1.7 MAX 1.4 0.1 B A 144 0.5 1 0.22 0.05 36 0.08 M 37 (21.0) 0.22 0.05 (0.2) 0 to 10 DETAIL A 0.5 0.15 DETAIL B (0.15) 0.15 0.05 0.1 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L051 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 160 - |
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